The Atmel ATF1504AS(L) is a high-performance, high-density Complex Programmable Logic Device (CPLD) which utilizes the Atmel proven electrically-erasable memory technology. With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI, and classic PLDs. The ATF1504AS(L) enhanced routing switch matrices increases usable gate count and the odds of successful pin-locked design modifications.
The ATF1504AS(L) has up to 68 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset, or output enable. Each of these control signals can be selected for use individually within each macrocell.
Each of the 64 macrocells generates a buried feedback which goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term which goes to a regional bus. Cascade logic between macrocells in the ATF1504AS(L) allows fast, efficient generation of complex logic functions. The ATF1504AS(L) contains four such logic chains; each capable of creating sum term logic with a fan-in of up to 40 product terms.
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1504AS(L). Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessible regardless of the state of the security fuse.
The ATF1504AS(L) device is an In-System Programmable (ISP) device. It uses the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.
The ATF1504AS(L) offers the option of programming all input and I/O pins so the pin-keeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high-level or low-level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption.
The ATF1504AS(L) has several built-in speed and power management features. The ATF1504AS(L) contains circuitry which automatically puts the device into a low-power standby mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides proportional power savings for most applications running at system speeds below 5MHz. This feature may be selected as a device option.
To further reduce power, each ATF1504AS(L) macrocell has a Reduced Power bit feature. This feature allows individual macrocells to be configured for maximum power savings. This feature may be selected as a
MICROCHIP ATF1504AS-7JX44