TI TMS320C6678ACYPA
| Manufacturer | |
| MPN | TMS320C6678ACYPA |
| LCSC Part # | C1520529 |
| Packaging | FCBGA-841 |
| Customer # | |
| Key Attributes | Multicore Fixed and Floating-Point Digital Signal Processor |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/DSP (Digital Signal Processors) | |
| Manufacturer | TI | |
| Packaging | FCBGA-841 | |
| ROM Size | - | |
| Operating Temperature | -40℃~+100℃ | |
| Voltage - Supply | - | |
| Features | Hardware MAC acceleration;Multi-core cooperative processing;DMA data transfer;High-speed peripheral interface;RTC and timer;Secure storage and protection | |
| Maximum Speed | 1GHz | |
| FLASH Size | - |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 44 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The TMS320C6678 DSP is a highest-performance fixed/floating-point DSP that is based on TI's KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 1.4 GHz. For developers of a broad range of applications, such as mission-critical systems, medical imaging, test and automation, and other applications requiring high performance, TI's TMS320C6678 DSP offers 11.2 GHz cumulative DSP and enables a platform that is power-efficient and easy to use. In addition, it is fully backward compatible with all existing C6000 family fixed and floating point DSPs.
TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intra-device and inter-device communication that allows the various DSP resources to operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a non-blocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.
For fixed-point use, the C66x core has 4x the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating point capability and the per-core raw computational performance in an industry-leading 44.8 GMACS/core and 22.4 GFLOPS/core (O1.4 GHz operating frequency). It can execute 8 single-precision floating point MAC operations per cycle and can perform double- and mixed-precision operations, and is IEEE754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backwards code-compatible with TI's previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to
Features
- Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each with – 1.0 GHz, 1.25 GHz, or 1.4 GHz C66x Fixed/Floating-Point CPU Core › 44.8 GMAC/Core for Fixed Point ⊙1.4 GHz › 22.4 GFLOP/Core for Floating Point ⊙ 1.4 GHz
- Memory › 32K Byte L1P Per Core 32K Byte L1D Per Core 512K Byte Local L2 Per Core
- Multicore Shared Memory Controller (MSMC) – 4096KB MSM SRAM Memory Shared by Eight DSP C66x CorePacs Memory Protection Unit for Both MSM SRAM and DDR3_EMIF
- Multicore Navigator – 8192 Multipurpose Hardware Queues with Queue Manager – Packet-Based DMA for Zero-Overhead Transfers
- Network Coprocessor – Packet Accelerator Enables Support for › Transport Plane IPsec, GTP-U, SCTP, PDCP L2 User Plane PDCP (RoHC, Air Ciphering) 1-Gbps Wire-Speed Throughput at 1.5 MPackets Per Second
- Peripherals – Four Lanes of SRIO 2.1 › 1.24/2.5/3.125/5 GBaud Operation Supported Per Lane › Supports Direct I/O, Message Passing › Supports Four 1x, Two 2x, One 4x, and Two 1x + One 2x Link Configurations
- PCIe Gen2 › Single Port Supporting 1 or 2 Lanes › Supports Up To 5 GBaud Per Lane
- HyperLink › Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability › Supports up to 50 Gbaud
- Gigabit Ethernet (GbE) Switch Subsystem › Two SGMII Ports › Supports 10/100/1000 Mbps Operation
- 64-Bit DDR3 Interface (DDR3-1600) › 8G Byte Addressable Memory Space
- 16-Bit EMIF
- Two Telecom Serial Ports (TSIP) › Supports 1024 DS0s Per TSIP › Supports 2/4/8 Lanes at 32.768/16.384/8.192 Mbps Per Lane
- UART Interface
- I2C Interface
- 16 GPIO Pins
- SPI Interface
- Semaphore Module
- Sixteen 64-Bit Timers
- Three On-Chip PLLs
- Commercial Temperature: – 0℃ to 85℃
- Extended Temperature: – -40℃ to 100℃
Applications
- Mission-Critical Systems
- High-Performance Computing Systems
- Communications
- Audio
- Video Infrastructure
- Imaging
- Analytics
- Networking
- Media Processing
- Industrial Automation
- Automation and Process Control
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 226.3587 | $ 226.36 |
| 30+ | $ 214.3074 | $ 6429.22 |
Standard Packaging44/Full Tray | ||
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 5A991B4A |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 5A991B4A |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |

