SILICON LABS SI5328C-C-GM
| Manufacturer | |
| MPN | SI5328C-C-GM |
| LCSC Part # | C1520225 |
| Packaging | QFN-36-EP(6x6) |
| Customer # | |
| Key Attributes | QFN-36-EP(6x6) Application Specific Clock/Timing RoHS |
| Datasheet |  SILICON LABS SI5328C-C-GM |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Manufacturer | SILICON LABS | |
| Packaging | QFN-36-EP(6x6) | |
| Features | Programmable clock output;Alarm function |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 490 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The Si5328 is a jitter-attenuating precision clock multiplier for Synchronous Ethernet applications requiring sub 1 ps jitter performance and ultra-low loop bandwidth. When combined with a low-wander, low-jitter reference oscillator, the Si5328 meets all of the wander, MTIE, TDEV, and other requirements listed in ITU-T G.8262/Y.1362. The Si5328 accepts two input clocks ranging from 8 kHz to 710 MHz and generates two output clocks ranging from 8 kHz to 808 MHz. The two outputs are divided down separately from a common source. The Si5328 can also use the TCXO as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The Si5328 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5328 is based on Silicon Laboratories' third-generation DSPLL technology, which provides frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 2.5 or 3.3 V supply, the Si5328 is ideal for providing clock multiplication and jitter attenuation in high-performance, Synchronous Ethernet timing applications.
Features
- Fully-compliant with ITU-T G.8262, EEC options 1 and 2.
- Generates any frequency from 8 kHz to 808 MHz.
- Ultra-low jitter clock outputs with jitter generation as low as 0.3 ps rms (12 kHz - 20 MHz)
- Integrated loop filter with selectable loop bandwidth (0.1 Hz; 1 to 10 Hz)
- Dual clock inputs with manual or automatically controlled hitless switching
- Dual clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS)
- LOL, LOS, FOS alarm outputs
- I2C or SPI programmable
- On-chip voltage regulator for 2.5 ± 10% or 3.3 V ± 10% operation
- Small size: 6 x 6 mm 36-lead QFN
- Pb-free, ROHS compliant
Applications
- G.8262 Synchronous Ethernet, EEC options 1 and 2
- GbE/10GbE/100GbE Synchronous Ethernet
- Carrier Ethernet switches, routers
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 30.1047 | $ 30.10 |
| 30+ | $ 28.6198 | $ 858.59 |
Standard Packaging490/Full Tray | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Manufacturer | SILICON LABS | |
| Packaging | QFN-36-EP(6x6) | |
| Features | Programmable clock output;Alarm function |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 490 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The Si5328 is a jitter-attenuating precision clock multiplier for Synchronous Ethernet applications requiring sub 1 ps jitter performance and ultra-low loop bandwidth. When combined with a low-wander, low-jitter reference oscillator, the Si5328 meets all of the wander, MTIE, TDEV, and other requirements listed in ITU-T G.8262/Y.1362. The Si5328 accepts two input clocks ranging from 8 kHz to 710 MHz and generates two output clocks ranging from 8 kHz to 808 MHz. The two outputs are divided down separately from a common source. The Si5328 can also use the TCXO as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The Si5328 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5328 is based on Silicon Laboratories' third-generation DSPLL technology, which provides frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 2.5 or 3.3 V supply, the Si5328 is ideal for providing clock multiplication and jitter attenuation in high-performance, Synchronous Ethernet timing applications.
Features
- Fully-compliant with ITU-T G.8262, EEC options 1 and 2.
- Generates any frequency from 8 kHz to 808 MHz.
- Ultra-low jitter clock outputs with jitter generation as low as 0.3 ps rms (12 kHz - 20 MHz)
- Integrated loop filter with selectable loop bandwidth (0.1 Hz; 1 to 10 Hz)
- Dual clock inputs with manual or automatically controlled hitless switching
- Dual clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS)
- LOL, LOS, FOS alarm outputs
- I2C or SPI programmable
- On-chip voltage regulator for 2.5 ± 10% or 3.3 V ± 10% operation
- Small size: 6 x 6 mm 36-lead QFN
- Pb-free, ROHS compliant
Applications
- G.8262 Synchronous Ethernet, EEC options 1 and 2
- GbE/10GbE/100GbE Synchronous Ethernet
- Carrier Ethernet switches, routers
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |