The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.
There is flexible ×9/×18 bus matching on both read and write ports.
The period required by the retransmit operation is fixed and short.
The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short.
These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during the master-reset cycle.
The input port is controlled by write-clock (WCLK) and write-enable (WEN(overline)) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. An output-enable (OE(overline)) input is provided for 3-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals can vary from 0 to fMAX, with complete independence.
There are no restrictions on the frequency of one clock input with respect to the other.
There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode.
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN for access. The state of the FWFT/SI input during master reset determines the timing mode in use.
In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines.
For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins: empty flag or output ready (EF/OR), full flag or input ready (FF(overline)/IR(overline)), half-full flag (HF(overline)), programmable almost-empty flag (PAE), and programmable almost-full flag (PAF(overline)). The IR and OR functions are selected in FWFT mode. The EF and FF(overline) functions are selected in standard mode. HF, PAE, and PAF always are available for use, regardless of timing mode.
PAE and PAF(overline) can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings also are provided, so that PAE can be set to switch at a predefined number of locations from the empty boundary. The PAF threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of FSEL0, FSEL1, and LD.
For serial programming, SEN, together with LD, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN, together with LD, loads the offset registers via Dn on each rising edge of WCLK. REN, together with LD, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial or parallel offset loading has been selected.
TI SN74V293-6PZA