MICROCHIP AT89LP52-20MU

The AT89LP51/52 is a low-power, high-performance CMOS 8-bit microcontroller with 4K/8K bytes of In-System Programmable Flash program memory and 256 bytes of Flash data memory. The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard 80C52 instruction set. The AT89LP51/52 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP51/52 CPU, instructions need only 1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051. Seventy percent of instructions need only as many clock cycles as they have bytes to execute, and most of the remaining instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reducing power consumption and EMI. The AT89LP51/52 also includes a compatibility mode that will enable classic 12 clock per machine cycle operation for true timing compatibility with AT89S51/52. The AT89LP51/52 provides the following standard features: 4K/8K bytes of In-System Programmable Flash program memory, 256 bytes of Flash data memory, 256 bytes of RAM, up to 36 I/O lines, three 16-bit timer/counters, a programmable watchdog timer, a full-duplex serial port, an on-chip crystal oscillator, an internal 1.8432 MHz auxiliary oscillator, and a four-level, six-vector interrupt system.

• 8-bit Microcontroller Compatible with 8051 Products
• Enhanced 8051 Architecture – Single Clock Cycle per Byte Fetch – 12 Clock per Machine Cycle Compatibility Mode – Up to 20 MIPS Throughput at 20 MHz Clock Frequency – Fully Static Operation: 0 Hz to 20 MHz – On-chip 2-cycle Hardware Multiplier – 256 x 8 Internal RAM – External Data/Program Memory Interface – Dual Data Pointers – 4-level Interrupt Priority
• Nonvolatile Program and Data Memory – 4K/8K Bytes of In-System Programmable (ISP) Flash Program Memory – 256 Bytes of Flash Data Memory – 256-byte User Signature Array – Endurance: 10,000 Write/Erase Cycles – Serial Interface for Program Downloading – 64-byte Fast Page Programming Mode – 3-level Program Memory Lock for Software Security – In-Application Programming of Program Memory
• Peripheral Features – Three 16-bit Timer/Counters with Clock Out Modes – Enhanced UART • Automatic Address Recognition • Framing Error Detection • SPI and TWI Emulation Modes
• Brown-out Detection and Power-on Reset with Power-off Flag – Selectable Polarity External Reset Pin – Low Power Idle and Power-down Modes – Interrupt Recovery from Power-down Mode – Internal 1.8432 MHz Auxiliary Oscillator
• Configurable Port Modes (per 8-bit port) • Quasi-bidirectional (80C51 Style) • Input-only (Tristate) • Push-pull CMOS Output • Open-drain
• Operating Conditions – 2.4V to 5.5V Vcc Voltage Range – -40℃ to 85℃ Temperature Range – 0 to 20 MHz @ 2.4V–5.5V – 0 to 25 MHz @ 4.5V–5.5V