TI CD4044BDR
| Manufacturer | |
| MPN | CD4044BDR |
| LCSC Part # | C133986 |
| Packaging | SOIC-16 |
| Customer # | |
| Key Attributes | CMOS Quad 3-State R/S Latches |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | TI | |
| Packaging | SOIC-16 | |
| Logic Type | SR Latch | |
| Voltage - Supply | 3V~18V | |
| Output Type | Tri-State | |
| Current - Output Low(IOL) | 4.2mA | |
| Operating Temperature | -55℃~+125℃ | |
| Current - Output High(IOH) | 4.2mA | |
| Number of Channels | 4 | |
| Propagation Delay | 50ns | |
| Quiescent Current (Iq) | 0.02uA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
CD4043B types are quad crosscoupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch.states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.
Features
- 3-state outputs with common output ENABLE
- Separate SET and RESET inputs for each latch
- NOR and NAND configurations
- 5-V, 10-V, and 15-V parametric ratings
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at μ20νν
- Maximum input current of μμ at 78ν over full package temperature range; 100 nA at 18 V and z5℃
- Noise margin (over full package temperature range): 1 V at ΔDD = 5V, 2V at VDD = 10V, 2.5νV at vDD = 15V
- Meets all requirements of JEDEC Tentative Standard No. 1aB, "Standard Specifications for Description of B′ Series CMOS Devices"
- Holding register in multi-register system
- Four bits of independent storage with output ENABLE
- Strobed register
- General digital logic
- CD4643B for positive logic systems
- CD4044B for negative logic systems
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.6345 | $ 0.63 |
| 10+ | $ 0.5193 | $ 5.19 |
| 30+ | $ 0.4609 | $ 13.83 |
| 100+ | $ 0.4025 | $ 40.25 |
| 500+ | $ 0.3684 | $ 184.20 |
| 1,000+ | $ 0.3132 | $ 313.20 |
Standard Packaging2500/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | TI | |
| Packaging | SOIC-16 | |
| Logic Type | SR Latch | |
| Voltage - Supply | 3V~18V | |
| Output Type | Tri-State | |
| Current - Output Low(IOL) | 4.2mA | |
| Operating Temperature | -55℃~+125℃ | |
| Current - Output High(IOH) | 4.2mA | |
| Number of Channels | 4 | |
| Propagation Delay | 50ns | |
| Quiescent Current (Iq) | 0.02uA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
CD4043B types are quad crosscoupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch.states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.
Features
- 3-state outputs with common output ENABLE
- Separate SET and RESET inputs for each latch
- NOR and NAND configurations
- 5-V, 10-V, and 15-V parametric ratings
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at μ20νν
- Maximum input current of μμ at 78ν over full package temperature range; 100 nA at 18 V and z5℃
- Noise margin (over full package temperature range): 1 V at ΔDD = 5V, 2V at VDD = 10V, 2.5νV at vDD = 15V
- Meets all requirements of JEDEC Tentative Standard No. 1aB, "Standard Specifications for Description of B′ Series CMOS Devices"
- Holding register in multi-register system
- Four bits of independent storage with output ENABLE
- Strobed register
- General digital logic
- CD4643B for positive logic systems
- CD4044B for negative logic systems
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



