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ST STM32H745XIH6
| Manufacturer | |
| MPN | STM32H745XIH6 |
| LCSC Part # | C1338373 |
| Packaging | TFBGA-265 |
| Customer # | |
| Key Attributes | Dual 32-bit Arm Cortex-M7 and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS |
| Datasheet |  ST STM32H745XIH6 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | ST | |
| Packaging | TFBGA-265 | |
| DAC (Bit) | 12bit | |
| ADC (Bit) | 16bit | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 1.62V~3.6V | |
| Program Memory Type | FLASH | |
| EEPROM | - | |
| Program Storage Size | 2MB | |
| CPU Core | ARM Cortex-M4;ARM Cortex-M7 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 240MHz;480MHz | |
| Oscillator Type | Built-in | |
| Number of I/O | 168 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 119 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Dual core: 32-bit Arm Cortex-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions. 32-bit Arm Cortex-M4 core with FPU, Adaptive real-time accelerator (ART Accelerator) for internal Flash memory and external memories, frequency up to 240 MHz, MPU, 300 DMIPS/1.25 DMIPS /MHz (Dhrystone 2.1), and DSP instructions
- Memories: Up to 2 Mbytes of Flash memory with read-while-write support. 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain. Dual mode Quad-SPI memory interface running up to 133 MHz. Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memory clocked up to 125 MHz in Synchronous mode. CRC calculation unit
- Security: ROP, PC-ROP, active tamper
- General-purpose input/outputs: Up to 168 l/O ports with interrupt capability
- Reset and power management: 3 separate power domains which can be independently clock-gated or switched off: D1: high-performance capabilities, D2: communication peripherals and timers, D3: reset/clock control/power management. 1.62 to 3.6 V application supply and I/Os. POR, PDR, PVD and BOR. Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs. Embedded regulator (LDO) to supply the digital circuitry. High power-efficiency SMPS step-down converter regulator to directly supply VCORE and/or external circuitry. Voltage scaling in Run and Stop mode (6 configurable ranges). Backup regulator (∼0.9 V). Voltage reference for analog peripheral/VREF+. 1.2 to 3.6 V BAT supply. Low-power modes: Sleep, Stop, Standby and V BAT supporting battery charging
- Low-power consumption: V BAT battery operating mode with charging capability. CPU and domain power state monitoring pins. 2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON)
- Clock management: Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI. External oscillators: 4 - 48 MHz HSE, 32.768 kHz LSE. 3× PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode
- Interconnect matrix: 3 bus matrices (1 AXI and 2 AHB). Bridges (5× AHB2 - APB, 2× AXI2 - AHB)
- 4 DMA controllers to unload the CPU: 1× high-speed master direct memory access controller (MDMA) with linked list support. 2× dual-port DMAs with FIFO. 1× basic DMA with request router capabilities
- Up to 35 communication peripherals: 4× I2Cs FM+ interfaces (SMBus/PMBus). 4× USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1× LPUART. 6× SPIs, 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1× 125 in LP domain (up to 150 MHz). 4× SAIs (serial audio interface). SPDIFRX interface. SWPMI single-wire protocol master I/F. MDIO Slave interface. 2× SD/SDIO/MMC interfaces (up to 125 MHz). 2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT - CAN). 2× USB OTG interfaces (1FS, 1HS/FS) crystalless solution with LPM and BCD. Ethernet MAC interface with DMA controller. HDMI - CEC. 8 - to 14-bit camera interface (up to 80 MHz)
- 11 analog peripherals: 3× ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS). 1× temperature sensor. 2× 12-bit D/A converters (1 MHz). 2× ultra-low-power comparators. 2× operational amplifiers (7.3 MHz bandwidth). 1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters
- Graphics: LCD - TFT controller up to XGA resolution. Chrom - ART graphical hardware Accelerator (DMA2D) to reduce CPU load. Hardware JPEG Codec
- Up to 22 timers and watchdogs: 1× high-resolution timer (2.1 ns max resolution). 2×32 - bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 240 MHz). 2×16 - bit advanced motor control timers (up to 240 MHz). 10× 16-bit general-purpose timers (up to 240 MHz). 5× 16-bit low-power timers (up to 240 MHz). 4× watchdogs (independent and window). 2× SysTick timers. RTC with sub-second accuracy and hardware calendar
- Debug mode: SWD & JTAG interfaces. 4 - Kbyte Embedded Trace Buffer
- True random number generators (3 oscillators each)
- 96-bit unique ID
- Optional support of extended temperature range up to 125 ℃ (specific part numbers)
- All packages are ECOPACK2 compliant
In-Stock: 200
200 In stock, ships now
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| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 12.0036 | $ 12.00 |
| 10+ | $ 10.5345 | $ 105.35 |
| 30+ | $ 9.6378 | $ 289.13 |
| 100+ | $ 8.8861 | $ 888.61 |
Standard Packaging119/Full Tray | ||
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | ST | |
| Packaging | TFBGA-265 | |
| DAC (Bit) | 12bit | |
| ADC (Bit) | 16bit | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 1.62V~3.6V | |
| Program Memory Type | FLASH | |
| EEPROM | - | |
| Program Storage Size | 2MB | |
| CPU Core | ARM Cortex-M4;ARM Cortex-M7 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 240MHz;480MHz | |
| Oscillator Type | Built-in | |
| Number of I/O | 168 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 119 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Dual core: 32-bit Arm Cortex-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions. 32-bit Arm Cortex-M4 core with FPU, Adaptive real-time accelerator (ART Accelerator) for internal Flash memory and external memories, frequency up to 240 MHz, MPU, 300 DMIPS/1.25 DMIPS /MHz (Dhrystone 2.1), and DSP instructions
- Memories: Up to 2 Mbytes of Flash memory with read-while-write support. 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain. Dual mode Quad-SPI memory interface running up to 133 MHz. Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memory clocked up to 125 MHz in Synchronous mode. CRC calculation unit
- Security: ROP, PC-ROP, active tamper
- General-purpose input/outputs: Up to 168 l/O ports with interrupt capability
- Reset and power management: 3 separate power domains which can be independently clock-gated or switched off: D1: high-performance capabilities, D2: communication peripherals and timers, D3: reset/clock control/power management. 1.62 to 3.6 V application supply and I/Os. POR, PDR, PVD and BOR. Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs. Embedded regulator (LDO) to supply the digital circuitry. High power-efficiency SMPS step-down converter regulator to directly supply VCORE and/or external circuitry. Voltage scaling in Run and Stop mode (6 configurable ranges). Backup regulator (∼0.9 V). Voltage reference for analog peripheral/VREF+. 1.2 to 3.6 V BAT supply. Low-power modes: Sleep, Stop, Standby and V BAT supporting battery charging
- Low-power consumption: V BAT battery operating mode with charging capability. CPU and domain power state monitoring pins. 2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON)
- Clock management: Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI. External oscillators: 4 - 48 MHz HSE, 32.768 kHz LSE. 3× PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode
- Interconnect matrix: 3 bus matrices (1 AXI and 2 AHB). Bridges (5× AHB2 - APB, 2× AXI2 - AHB)
- 4 DMA controllers to unload the CPU: 1× high-speed master direct memory access controller (MDMA) with linked list support. 2× dual-port DMAs with FIFO. 1× basic DMA with request router capabilities
- Up to 35 communication peripherals: 4× I2Cs FM+ interfaces (SMBus/PMBus). 4× USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1× LPUART. 6× SPIs, 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1× 125 in LP domain (up to 150 MHz). 4× SAIs (serial audio interface). SPDIFRX interface. SWPMI single-wire protocol master I/F. MDIO Slave interface. 2× SD/SDIO/MMC interfaces (up to 125 MHz). 2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT - CAN). 2× USB OTG interfaces (1FS, 1HS/FS) crystalless solution with LPM and BCD. Ethernet MAC interface with DMA controller. HDMI - CEC. 8 - to 14-bit camera interface (up to 80 MHz)
- 11 analog peripherals: 3× ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS). 1× temperature sensor. 2× 12-bit D/A converters (1 MHz). 2× ultra-low-power comparators. 2× operational amplifiers (7.3 MHz bandwidth). 1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters
- Graphics: LCD - TFT controller up to XGA resolution. Chrom - ART graphical hardware Accelerator (DMA2D) to reduce CPU load. Hardware JPEG Codec
- Up to 22 timers and watchdogs: 1× high-resolution timer (2.1 ns max resolution). 2×32 - bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 240 MHz). 2×16 - bit advanced motor control timers (up to 240 MHz). 10× 16-bit general-purpose timers (up to 240 MHz). 5× 16-bit low-power timers (up to 240 MHz). 4× watchdogs (independent and window). 2× SysTick timers. RTC with sub-second accuracy and hardware calendar
- Debug mode: SWD & JTAG interfaces. 4 - Kbyte Embedded Trace Buffer
- True random number generators (3 oscillators each)
- 96-bit unique ID
- Optional support of extended temperature range up to 125 ℃ (specific part numbers)
- All packages are ECOPACK2 compliant
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |