TI CD4099BM96

CD4099B 8-bit addressable latch Is a serial-input, parallel-output storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and, when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic 0 level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input; while all unaddressed bits are held to a logic 0 level.

• Serial data input
• Active parallel output
• Storage register capability
• Master clear
• Can function as demultiplexer
• Standardized, symmetrical output characteristics
• 700% tested for quiescent current at 20 V
• Maximum input current of ±1μA at 18 V (full package-temperature range), 100 nA at 18 V and 25℃
• Noise margin (full package-temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative - Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

• Multi-line decoders
• A/D converters