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TI TPS51100DGQRRoHS

Manufacturer
MPN
TPS51100DGQR
LCSC Part #
C131927
Packaging
MSOP-10-EP
Customer #
Key Attributes
3-A Sink/Source DDR Termination Regulator
Datasheetpdf iconTI TPS51100DGQR

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Power Management (PMIC)/Special Purpose Regulators
ManufacturerTI
PackagingMSOP-10-EP
FeaturesOutput voltage tracking;Cable compensation;Overcurrent Protection;Output discharge

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2500
Sales UnitPiece

Introduction

AI Translation

Input Voltage Range: 4.75 V to 5.25 V VLDOIN Voltage Range: 1.2 V to 3.6 V 3-A Sink/Source Termination Regulator Includes Droop Compensation Requires Only 20-μF Ceramic Output Capacitance Supports Hi-Z in S3 and Soft-Off in S5 1.2-V Input (VLDOIN) Helps Reduce Total Power Dissipation Integrated Divider Tracks 0.5 VDDQSNS for VTT and VTTREF Remote Sensing (VTTSNS) ±20 mV Accuracy for VTT and VTTREF 10-mA Buffered Reference (VTTREF) • Built-In Soft-Start, UVLO, and OCL Thermal Shutdown Supports JEDEC Specifications

Features

AI Translation
  • Input Voltage Range: 4.75 V to 5.25 V
  • VLDOIN Voltage Range: 1.2 V to 3.6 V
  • 3-A Sink/Source Termination Regulator
  • Includes Droop Compensation
  • Requires Only 20-μF Ceramic Output Capacitance
  • Supports Hi-Z in S3 and Soft-Off in S5
  • 1.2-V Input (VLDOIN) Helps Reduce Total Power Dissipation
  • Integrated Divider Tracks 0.5 VDDQSNS for VTT and VTTREF
  • Remote Sensing (VTTSNS) ±20 mV Accuracy for VTT and VTTREF
  • 10-mA Buffered Reference (VTTREF)
  • Built-In Soft-Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports JEDEC Specifications

Applications

AI Translation
  • DDR, DDR2, DDR3 Memory Termination
  • SSTL-2, SSTL-18, and HSTL Termination
In-Stock: 7,286
7,286 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 0.9023$ 0.90
10+$ 0.7859$ 7.86
30+$ 0.7358$ 22.07
100+$ 0.6727$ 67.27
500+$ 0.4431$ 221.55
1,000+$ 0.4269$ 426.90
Standard Packaging2500/Full Reel
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