TI TCA4311ADGKR

Hot-pluggable I2C bus buffer, which supports the plugging and unplugging operations of I/O boards on live backplanes without damaging the data and clock buses. The control circuit can prevent the backplane from connecting to the board (until a stop command appears on the backplane or the bus is idle), without causing bus contention on the board. When the connection is established, the device provides bidirectional buffering to keep the backplane and board capacitances isolated. During the board insertion process, the SDA and SCL lines are precharged to 1V to minimize the current required to charge the parasitic capacitance of the chip. When the I2C bus is idle, the TCA4311A can be placed in the shutdown mode by setting the EN pin to a low level. When the EN pin is at a high level, the TCA4311 resumes normal operation. The device also includes an open-drain READY output pin, which is responsible for giving an indication signal when the backplane is connected to the board side. When the READY pin is at a high level, SDAIN and SCLIN are connected to SDAOUT and SCLOUT. When the two sides are disconnected, the READY pin is at a low level. Both the backplane and the board can be powered by a supply voltage of 2.7V to 5.5V, and there is no restriction on which one has a higher supply voltage. The TCA4311 has standard open-drain I/Os. The size of the pull-up resistor to the I/O depends on the system. However, each side of the buffer must have a pull-up resistor. This device is designed to work with standard-mode and fast-mode I2C devices (not just SMBus devices). In a general-purpose I2C system that can accept standard-mode devices and multiple masters, the standard-mode I2C device only specifies 3mA. Under certain conditions, a high termination current can be used.

• Operating supply voltage range: 2.7V to 5.5V
• Bidirectional data transfer supporting I²C bus signals
• Buffered SDA and SCL lines for increased fanout
• 1-V precharge on all SDA and SCL lines to prevent damage during hot insertion/removal of boards on backplane
• SDA and SCL inputs isolated from outputs
• Compatible with standard-mode and fast-mode I2C devices
• Improved noise immunity
• Low Icc chip disable mode: <1 μA
• READY open-drain output
• Supports clock stretching, arbitration, and synchronization
• Power-off high-impedance pins
• Open-drain pins
• Latch-up performance exceeds 100 mA (per JESD 78, Class II)
• ESD protection exceeds JESD 22: 8000-V HBM (A114-A), 200-V MM (A115-A), 1000-V CDM (C101)