MICROCHIP MCP37221-200E/TE

The MCP37231/21-200 is a 16-/14-bit 200 Msps pipelined ADC family, featuring built-in high-order digital decimation filters, gain and offset adjustment per channel and fractional delay recovery. The MCP37D31/21-200 device family features digital down-conversion and CW beamforming capability, in addition to the features offered by the MCP37231/21- 200. All devices feature harmonic distortion correction and DAC noise cancellation that enable high-performance specifications with SNR of 74.7 dBFS (typical), and SFDR of 90 dBc (typical). These A/D converters exhibit industry-leading low-power performance with only 490 mW operation while using the LVDS interface at 200 Msps. This superior low-power operation coupled with high dynamic performance makes these devices ideal for various high-performance, high-speed data acquisition systems, including communications equipment, radar and portable instrumentation. The output decimation filter option improves SNR performance up to 93.5 dBFS with the 512x decimation setting. The digital down-conversion option, in conjunction with the decimation and quadrature output options, offers great flexibility in digital communication system design, including cellular base-stations and narrow-band communications. Gain, phase and DC offset can be adjusted independently for each input channel, allowing for simplified implementation of CW beamforming and ultrasound Doppler imaging applications. These devices can have up to eight differential input channels through an input MUX. The sampling rate is up to 200 Msps when a single channel is used, or 25 Msps per channel when all eight input channels are used. In dual or octal-channel mode, the Fractional Delay Recovery (FDR) feature digitally corrects the difference in sampling instance between different channels, so that all inputs appear to have been sampled at the same time. The device samples the analog input on the rising edge of the clock. The digital output code is available after 28 clock cycles of data latency. Latency will increase if any of the digital signal post-processing (DSPP) options are enabled. AutoSync mode offers a great design flexibility when multiple devices are used in applications. It allows multiple devices to sample input synchronously at the same clock. The differential full-scale analog input range is programmable up to 2.975 Vp-p. The ADC output data can be coded in two's complement or offset binary representation, with or without the data randomizer option. The output data is available as full-rate CMOS or Double-Data-Rate (DDR) LVDS. Additionally, a serialized LVDS option is also available for the 16-bit octal-channel mode. These devices also include various features designed to maximize flexibility in the user’s applications and minimize system cost, such as a programmable PLL clock, output data rate control and phase alignment and programmable digital pattern generation.

• Sample Rates: - 200 Msps for single-channel mode - 200 Msps/number of channels used
• SNR with fIN = 15 MHz and -1 dBFS: - 74.7 dBFS (typical) at 200 Msps
• SFDR with fIN = 15 MHz and -1 dBFS: - 90 dBc (typical) at 200 Msps
• Power Dissipation with LVDS Digital I/O: - 490 mW at 200 Msps
• Power Dissipation with CMOS Digital I/O: - 436 mW at 200 Msps, Output Clock = 100 MHz
• Power Dissipation Excluding Digital I/O: - 390 mW at 200 Msps
• Power-Saving Modes: - 144 mW during Standby - 28 mW during Shutdown
• Supply Voltage: - Digital Section: 1.2V, 1.8V - Analog Section: 1.2V, 1.8V
• Selectable Full-Scale Input Range: up to 2.975 Vp-p
• Input Channel Bandwidth: 500 MHz
• Channel-to-Channel Crosstalk in Multi-Channel Mode (fIN = 15 MHz, -1 dBFS): >95 dB
• Output Data Format: - Parallel CMOS, DDR LVDS - Serialized DDR LVDS (16-bit, octal-channel mode)
• Optional Output Data Randomizer
• Built-In ADC Linearity Calibration Algorithms: - Harmonic Distortion Correction (HDC) - DAC Noise Cancellation (DNC) - Dynamic Element Matching (DEM) - Flash Error Calibration
• Digital Signal Post-Processing (DSPP) Options: - Decimation filters for improved SNR - Fractional Delay Recovery (FDR) for time delay corrections in multi-channel operations (dual-/octal-channel modes) - Phase, Offset and Gain adjust of individual channels - Digital Down-Conversion (DDC) with I/Q or fS/8 output (MCP37D31/21-200) - Continuous wave beamforming for octal-channel mode (MCP37D31/21-200)
• Serial Peripheral Interface (SPI)
• Auto Sync Mode to Synchronize Multiple Devices to the Same Clock
• AEC-Q100 Qualified (Automotive Applications)
• Package Options: (a) TFBGA-121 (8 mm x 8 mm x 1.08 mm): - AEC-Q100 qualified - Temperature Grade 1: -40°C to +125°C - Includes embedded decoupling capacitors for reference pins and bandgap output pin (b) VTLA-124 (9 mm x 9 mm x 0.9 mm) - Temperature Range: -40°C to +85°C

• Communication Instruments
• Cellular Base Stations
• Lidar and Radar
• Ultrasound and Sonar Imaging
• Scanners and Low-Power Portable Instruments
• Industrial and Consumer Data Acquisition System