MICROCHIP 48LM01-I/SM
| Manufacturer | |
| MPN | 48LM01-I/SM |
| LCSC Part # | C1161707 |
| Packaging | SOIC-8-208mil |
| Customer # | |
| Key Attributes | 1Mbit SOIC-8-208mil Specialized Memory Products RoHS |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Office Supplies/Storage Products/Specialized Memory Products | |
| Manufacturer | MICROCHIP | |
| Packaging | SOIC-8-208mil | |
| Supply Current (Icc) | 5mA | |
| Voltage - Supply | 2.7V~3.6V | |
| Operating Temperature | -40℃~+85℃ | |
| Features | Auto power-down function;Hardware write protection function | |
| Memory Size | 1Mbit | |
| Standby Current (Iq) | 200uA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 90 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 48L512/48LM01 (48LXXX) serial EERAM has an SRAM memory core with hidden EEPROM backup. The device can be treated by the user as a full symmetrical read/write SRAM. Backup to EEPROM is handled by the device on any power disrupt, so the user can effectively view this device as an SRAM that never loses its data. The device is structured as a 512/1024-Kbit SRAM with EEPROM backup in each memory cell. The SRAM is organized as 65,536x8 bits or 131,072x8 bits, and uses the SPI serial interface. The SPI bus uses three signal lines for communication: clock input (SCK), data in (SI), and data out (SO). Access to the device is controlled through a Chip Select (CS) input, allowing any number of devices to share the same bus. The SRAM is a conventional serial SRAM: it allows symmetrical reads and writes and has no limits on cell usage. The backup EEPROM is invisible to the user and cannot be accessed by the user independently. The device includes circuitry that detects VCC dropping below a certain threshold, shuts its connection to the outside environment, and transfers all SRAM data to the EEPROM portion of each cell for safe keeping. When VCC returns, the circuitry automatically returns the data to the SRAM and the user’s interaction with the SRAM can continue with the same data set.
Features
- Unlimited Reads/Unlimited Writes:
- Standard serial SRAM protocol - Symmetrical timing for reads and writes
- SRAM Array:
- 65,536x8 bit (48L512) - 131,072x8 bit (48LM01)
- High-Speed SPI Interface:
- Up to 66 MHz
- Schmitt Trigger inputs for noise suppression
- Low-Power CMOS Technology:
- Active current: 5 mA (maximum)
- Standby current: 200 μA (at 85℃ maximum)
- Hibernate current: 3 μA (at 85℃ maximum)
- Cell-Based Nonvolatile Backup:
- Mirrors SRAM array cell-for-cell
- Transfers all data to/from SRAM cells in parallel (all cells at same time)
- Invisible-to-User Data Transfers:
- VCC level monitored inside device
- SRAM automatically saved on power disrupt
- SRAM automatically restored on VCC return
- 100,000 Backups Minimum (at 85℃)
- 100 Years Retention (at 55℃)
- Operating Voltage Range: 2.7V - 3.6V
- Temperature Ranges:
- Industrial (I): -40℃ to +85℃
- ESD Protection: > 2,000
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |



