TI SN74V245-15PAGEP

The SN74V245 is an ultra-high-speed, low-power CMOS clocked first-in first-out (FIFO) memory. It supports clock frequencies up to 133MHz and features a fast read access time of 5ns. This DSP synchronous FIFO memory offers dedicated read and access control for applications such as DSP-to-processor communication, DSP-to-analog front-end (AFE) buffering, networking, video, and data communications.

The SN74V245 is a synchronous FIFO, meaning each port uses a synchronous interface. All data transferred through the ports is clocked on the low-to-high transitions of the free-running port clock, gated by an enable pin. The free-running clocks for each port are independent and may operate asynchronously or synchronously. The enable for each port can be configured to provide a simple interface between DSPs, microcontrollers, and/or buses controlled by a synchronous interface. An output enable (OE) input controls the 3-state outputs.

The synchronous FIFO provides two fixed flags — Empty Flag/Output Ready (EF/OR) and Full Flag/Input Ready (FF/IR) — and two programmable flags: Almost Empty (PAE) and Programmable Almost Full (PAF). The offset values for the programmable flags are controlled by a simple state machine and are initiated by asserting the Load pin (LD). A Half Full flag (HF) is available when the FIFO is used in a single-device configuration.

The SN74V245 supports two timing operating modes: First Word Fall Through (FWFT) mode and Standard mode.

In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. It is not necessary to assert a Read Enable (REN) to access the first word.

In Standard mode, the first word written to an empty FIFO does not appear on the output lines unless a specific read operation is performed. A read operation that asserts REN and enables a rising RCLK edge will move the word from internal memory to the data output lines.

The depth of the SN74V245 is expandable using daisy-chain techniques or FWFT mode. The XI and XO pins are used for FIFO expansion. In a depth expansion configuration, the First Load (FL̄) pin on the first device is tied to ground and set high for all other devices in the daisy chain.

The SN74V245 is rated for an operating temperature range of -55℃ to 125℃.

• 4096×18-bit organized array
• 7.5ns read and write cycle time
• 3.3V VCC, 5V input tolerant
• First word fall-through or standard flow-through timing
• Single or double registered empty and full flags
• Easily expandable depth and width
• Asynchronous or synchronous read and write clocks
• Asynchronous or synchronous programmable almost-empty and almost-full flags with default settings
• Half-full flag function
• Output enable places output data bus in high-impedance state
• High-performance submicron CMOS technology
• DSP and microcontroller interface control logic
• Provides a glueless DSP interface to Texas Instruments (TI) TMS320 DSP packaged in a 64-pin TQFP
• Controlled baseline
• Single assembly and test site
• Single fabrication site
• Supports -55°C to 125°C temperature range
• Extended product life cycle
• Extended product change notification
• Product traceability