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MaxLinear ST16C554DIQ64TR-F product image
  • ST16C554DIQ64TR-F thumbnail 1
  • ST16C554DIQ64TR-F thumbnail 2
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  • Pinout Diagram
  • Footprint Diagram
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MaxLinear ST16C554DIQ64TR-FRoHS

Manufacturer
MPN
ST16C554DIQ64TR-F
LCSC Part #
C11122
Packaging
TQFP-64(10x10)
Customer #
Key Attributes
ST16C554D Quad UART with 16-Byte FIFOs
Datasheetpdf iconMaxLinear ST16C554DIQ64TR-F

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Interface/UARTs (Universal Asynchronous Receiver Transmitter)
ManufacturerMaxLinear
PackagingTQFP-64(10x10)
FeaturesFractional baud rate generator;Internal loopback/self-test mode;Automatic error detection;with Modem Control
Data Rate1.5Mbps
Number of Channels4
Operating Temperature-40℃~+85℃
Voltage - Supply3.3V~5V

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging1000
Sales UnitPiece

Introduction

AI Translation

The ST16C554D isa universal asynchronous receiver and transmitter (UART) with a dual foot print interface. The 554D is an enhanced UART with 16 byte FIFOs, receive trigger levels and data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status, modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics. The 554D combines the package interface modes ofthe 16C554 and 68C554 series on a single integrated chip. The 554D provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-paralleldata conversions for both the transmitter and receiver sections. These functions are necessary for convertingtheserialdatastreamintoparalleldatathat is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The ST16C554D represents such an integration with greatly enhanced features. The 554D is fabricated withanadvanced CMoSprocesstoachievelow drain power and high speed requirements. The 554D is an upward solution that provides 16 bytes of transmit and receive FiFO memory, instead of 1 bytes provided in the 16/68C454. The 554D is designed toworkwith high speed modems and shared network environments, that require fast data processing time. Increased performance is realized in the 554D by the larger transmit and receive FIFOs. This allows the external processorto handle more networking tasks within a given time. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. The 554D combines the package interface modes of the 16C554D and 68C554 series on a single integrated chip. The 16 mode interface is designed to operate with the Intel type of microprocessor bus while the 68 mode is intended to operate with Motorola, and other popular microprocessors. Following a reset, the 554Dis down-wardcompatiblewith theST16C454/ ST68C454dependent on the state of theinterface mode selection pin, 16/-68. The 554D is capable of operation to 1.5Mbps with a 24 MHz crystal or external clock input. With a crystal of 14.7464 MHz, the user can select data rates up to 921.6Kbps.

Features

AI Translation
  • Compatibility with the Industry Standard ST16C454,ST68C454,ST68C554,TL16C554
  • 1.5 Mbps transmit/receive operation (24MHz)
  • 16 byte transmit FIFO
  • 16 byte receive FIFO with error flags
  • Independent transmit and receive control
  • Software selectable Baud Rate Generator
  • Four selectable Receive FIFO interrupt trigger levels
  • Standard modem interface
In-Stock: 139
139 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 4.9166$ 4.92
10+$ 4.1739$ 41.74
30+$ 3.7335$ 112.01
100+$ 3.2885$ 328.85
500+$ 3.0829$ 1541.45
1,000+$ 2.9893$ 2989.30
Standard Packaging1000/Full Reel
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