TI TMS320C5535AZAYA10

These devices are members of the TI C5000 fixed-point digital signal processor (DSP) product family, suitable for low-power applications.

The fixed-point DSP is based on the TMS320C55x DSP series CPU processor core. The C55x DSP architecture achieves high performance and low power consumption through increased parallelism and an emphasis on energy efficiency. The CPU supports an internal bus structure that includes a program bus, a 32-bit read bus, two 16-bit data read buses, two data write buses, and additional buses dedicated to peripheral and DMA operations. These buses enable the execution of up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing a data transfer environment with 16 independent channels without CPU intervention. Each DMA controller can perform a 32-bit data transfer per cycle, which is parallel to and independent of the CPU operation.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of performing a 17-bit by 17-bit multiplication and a 32-bit addition in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. The use of the ALU is controlled by the instruction set, providing the ability to optimize parallel operation and power consumption. The address unit (AU) and data unit (DU) within the C55x CPU manage these resources.

The C55x CPU supports a variable byte-width instruction set to improve code density. The instruction unit (IU) fetches instructions from the 32-bit program in internal or external memory and queues them for the program unit (PU). The PU decodes the instructions, directs tasks to the address unit and data unit resources, and manages a fully protected pipeline. The branch prediction function avoids pipeline flushing during conditional instruction execution.

The general input and output functions on the TMS320C5535, together with the 10-bit SAR ADC, provide sufficient pins for status, interrupts, and bit I/O for keyboard and media interfaces. Support for serial media is provided by the following devices: two Secure Digital (SD) peripherals, four Internal IC Sound (I2S bus) modules, a Serial Port Interface (SPI) with up to four chip selects, an I2C master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

Other peripherals include: a high-speed Universal Serial Bus (USB 2.0) supporting only device mode (not available on the TMS320C5532), a Real-Time Clock (RTC), three general-purpose timers (one of which can be configured as a watchdog timer), and an Analog Phase-Locked Loop (APLL) clock generator.

In addition, the TMS320C5535 also includes a tightly coupled FFT hardware accelerator. The tightly coupled FFT hardware accelerator supports 8 to 1024-point (powers of 2) real and complex FFTs.

The device also includes the following three integrated LDOs for powering various parts of the device:

ANA_LDO (all devices) provides 1.3V for the DSP PLL (VDDA_PLL), SAR, and power management circuit (VDDA_ANA).

DSP_LDO (TMS320C5535 and C5534) provides 1.3V or 1.05V for the DSP core (CVDD) (which can be selected in real-time by software once the operating frequency range is detected). In the lowest power consumption operating state, the programmer can turn off the internal DSP_LDO, cut off the power to the DSP core (CVDD), and power the RTC (CVDDRTC and DVDDRTC) from an external power source. The internal DSP_LDO can be re-enabled via the RTC alarm interrupt or the WAKEUP pin, and then the DSP core can be powered up again. After the DSP_LDO is reset, it can provide a 1.3V operating voltage for the boot loader. For 50MHz devices, the DSP_LDO must be set to 1.05V after reset to match the core voltage CVDD to ensure normal operation.

USB_LDO (TMS320C5535, C5534, and C5533) provides 1.3V for the USB core digital circuit (USB_VDD1P3) and the physical layer circuit (USB_VDDA1P3).

These devices are supported by the industry-acclaimed eXpressDSP, Code Composer Studio integrated development environment (IDE), DSP/BIOS, Texas Instruments' algorithm standards, and the largest third-party network in the industry. The code generation tools provided by the Code Composer Studio IDE include a C compiler and linker, RTDX, XDS100, XDS510, XDS560 emulation device drivers, and evaluation modules. These devices are also supported by the C55x DSP library and the chip support library, which features more than 50 basic software kernels (FIR filters, IIR filters, FFTs, and various mathematical functions).

• Core:
  • High-performance, low-power TMS320C55x fixed-point DSP
  • 20ns, 10ns instruction cycle time; 50MHz, 100MHz clock rate
  • One or two instructions executed per cycle
  • Two multiply-accumulate units (up to 200 MMACS)
  • Two ALUs
  • Three internal data/operand read buses and two internal data/operand write buses
  • Software compatible with C55x devices
  • Industrial temperature devices available
  • 320KB zero-wait-state on-chip RAM, including:
    • 64KB Dual-Access RAM (DARAM), 8 blocks of 4K × 16-bit
    • 256KB Single-Access RAM (SARAM), 32 blocks of 4K × 16-bit
  • 128KB zero-wait-state on-chip ROM (4 blocks of 16K × 16-bit)
  • Tightly coupled FFT hardware accelerator
• Peripherals:
  • DMA controller: four DMAs, each with four channels (16 channels total)
  • Three 32-bit GP timers, one configurable as watchdog or GP
  • Two eMMC and SD interfaces
  • UART
  • SPI with four chip selects
  • Master and slave I2C bus
  • Four I2S buses for data transfer
  • USB port with integrated USB 2.0 high-speed PHY, supporting USB 2.0 full-speed and high-speed device modes
  • LCD bridge with asynchronous interface
  • 10-bit, 4-input SAR ADC
  • IEEE-1149.1 (JTAG) boundary scan compatible
  • 32 GPIO pins (multiplexed with other device functions), up to 20 GPIO pins configurable simultaneously
• Power:
  • Four isolated core power domains: analog, RTC, CPU and peripherals, and USB
  • Three isolated I/O power domains: RTC I/O, USB PHY, and DVDDIO
  • Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) supplying isolated domains: DSP core, analog, and USB core respectively
  • 1.05V core (50MHz), 1.8V, 2.5V, 2.75V, or 3.3V I/O
  • 1.3V core (100MHz), 1.8V, 2.5V, 2.75V, or 3.3V I/O
• Clock:
  • RTC with crystal oscillator input, independent clock domain, and independent power supply
  • Low-power software-programmable PLL clock generator
• Bootloader:
  • On-chip ROM bootloader (RBL), supporting boot from SPI EEPROM, SPI serial flash, I2C EEPROM, eMMC, SD, SDHC, UART, and USB
• Package:
  • 144-terminal lead-free plastic BGA package (suffix ZHH)

• Wireless audio devices (e.g., headsets, microphones, hands-free phones)
• Echo-canceling headsets
• Portable medical devices
• Voice applications
• Industrial control
• Fingerprint recognition
• Software-defined radio