MICROCHIP 47L64-I/SN
| Manufacturer | |
| MPN | 47L64-I/SN |
| LCSC Part # | C1019376 |
| Packaging | SOIC-8 |
| Customer # | |
| Key Attributes | 64Kbit SOIC-8 Specialized Memory Products RoHS |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Office Supplies/Storage Products/Specialized Memory Products | |
| Manufacturer | MICROCHIP | |
| Packaging | SOIC-8 | |
| Supply Current (Icc) | 1mA | |
| Voltage - Supply | 2.7V~3.6V | |
| Operating Temperature | -40℃~+85℃ | |
| Features | Auto power-down function;Hardware write protection function | |
| Standby Current (Iq) | 200uA | |
| Memory Size | 64Kbit |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 100 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 47L64 serial EERAM has an SRAM memory core with hidden EEPROM backup. The device can be treated by the user as a full symmetrical read/write SRAM. Backup to EEPROM is handled by the device on any power disrupt, so the user can effectively view this device as an SRAM that never loses its data. The device is structured as a 64-Kbit SRAM with EEPROM backup in each memory cell. The SRAM is organized as 8,192x8 bits and uses the I²C serial interface. The I²C bus uses two signal lines for communication: clock input (SCL) and data (SDA). Access to the device is controlled through a chip address and address pins, allowing up to four devices to share the same bus. The SRAM is a conventional serial SRAM: it allows symmetrical reads and writes and has no limits on cell usage. The backup EEPROM is invisible to the user and cannot be accessed by the user independently. The device includes circuitry that detects VCC dropping below a certain threshold, shuts its connection to the outside environment, and transfers all SRAM data to the EEPROM portion of each cell for safe keeping. When VCC returns, the circuitry automatically returns the data to the SRAM and the user’s interaction with the SRAM can continue with the same data set.
Features
- Unlimited Reads/Unlimited Writes: Standard serial SRAM protocol, Symmetrical timing for reads and writes
- SRAM Array: 8,192x8 bits
- High-Speed I²C Interface: Industry standard: 1 MHz, 400 kHz, and 100 kHz, Zero cycle delay writes and reads to SRAM array, Schmitt Trigger inputs for noise suppression
- Low-Power CMOS Technology: Active current: 1 mA (maximum), Standby current: 200 μA (maximum)
- Cell-Based Nonvolatile Backup: Mirrors SRAM array cell-for-cell, Transfers all data to/from SRAM cells in parallel (all cells at same time)
- Invisible-to-User Data Transfers: VCC level monitored inside device, SRAM automatically saved on power disrupt, SRAM automatically restored on VCC return
- 100,000 Backups Minimum
- 100 Years Retention (at 55℃)
- Operating Voltage Range: 2.7V to 3.6V
- Temperature Ranges: Industrial (I): -40℃ to +85℃
- ESD protection: >2,000V
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 2.1599 | $ 2.16 |
| 10+ | $ 1.858 | $ 18.58 |
| 30+ | $ 1.6693 | $ 50.08 |
| 100+ | $ 1.4143 | $ 141.43 |
| 500+ | $ 1.3282 | $ 664.10 |
| 1,000+ | $ 1.289 | $ 1289.00 |
Standard Packaging100/Full Tube | ||
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |



