Infineon/CYPRESS CY8C4128LQI-BL543

PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm Cortex -M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4100_BLE product family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth Low Energy (BLE), also known as Bluetooth Smart, radio and subsystem (BLESS), compliant with Bluetooth 4.2 specifications. The other features include digital programmable logic, high - performance analog - to - digital conversion (ADC), opamps with comparator mode, and standard communication and timing peripherals. The PSoC 4100_BLE products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in - field tuning of the design.

• 32 - bit MCU Subsystem
  • 24 - MHz Arm Cortex - M0 CPU with single - cycle multiply
  • Up to 256 KB of flash with Read Accelerator
  • Up to 32 KB of SRAM
• BLE Radio and Subsystem
  • 2.4 - GHz RF transceiver with BLE 4.2 support and 50 - Ω antenna drive
  • Digital PHY
  • Link Layer engine supporting master and slave modes
  • RF output power: –18 dBm to +3 dBm
  • RX sensitivity: –89 dBm
  • RX current: 16.4 mA
  • TX current: 15.6 mA at 0 dBm
  • Received Signal Strength Indication (RSSI): 1 - dB resolution
• Programmable Analog
  • Two opamps with reconfigurable high - drive external and high - bandwidth internal drive, comparator modes, and ADC input buffering capability; can operate in Deep - Sleep mode.
  • 12 - bit, 806 ksps SAR ADC with differential and single - ended modes; channel sequencer with signal averaging
  • Two current DACs (IDACs) for general - purpose or capacitive sensing applications on any pin
  • Two low - power comparators that operate in Deep - Sleep mode
• Power Management
  • Active mode: 1.7 mA at 3 - MHz flash program execution
  • Deep - Sleep mode: 1.3 μA with watch crystal oscillator (WCO) on
  • Hibernate mode: 150 nA with RAM retention
  • Stop mode: 60 nA
• Capacitive Sensing
  • Cypress CapSense Sigma - Delta (CSD) provides best - in - class SNR (>5;1) and liquid tolerance
  • Cypress - supplied software component makes capacitive - sensing design easy
  • Automatic hardware - tuning algorithm (SmartSense™)
• Segment LCD Drive
  • LCD drive supported on all pins (common or segment)
  • Operates in Deep - Sleep mode with four bits per pin memory
• Serial Communication
  • Two independent runtime reconfigurable serial communication blocks (SCBs) with reconfigurable I²C, SPI, or UART functionality
• Timing and Pulse - Width Modulation
  • Four 16 - bit timer, counter, pulse - width modulator (TCPWM) blocks
  • Center - aligned, Edge, and Pseudo - random modes
  • Comparator - based triggering of Kill signals for motor drive and other high - reliability digital logic applications
• Up to 36 Programmable GPIOs
  • Any GPIO pin can be CapSense, LCD, analog, or digital
  • Two overvoltage - tolerant (OVT) pins; drive modes, strengths, and slew rates are programmable
• PSoC Creator™ Design Environment
  • Integrated design environment (IDE) provides schematic design entry and build (with analog and digital automatic routing)
  • API components for all fixed - function and programmable peripherals
• Industry - Standard Tool Compatibility
  • After schematic entry, development can be done with Arm - based industry - standard development tools