Intel/Altera EPM3128ATC100-10N

MAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM–based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the –4, -5, -6, -7, and -10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. The MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high–density small-scale integration (SSI), medium-scale integration (MSI), and large-scale integration (LSI) logic functions. The MAX 3000A architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 3000A devices are available in a wide range of packages, including PLCC, PQFP, and TQFP packages. MAX 3000A devices use CMOS EEPROM cells to implement logic functions. The user–configurable MAX 3000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debugging cycles, and can be programmed and erased up to 100 times. MAX 3000A devices contain 32 to 512 macrocells, combined into groups of 16 macrocells called logic array blocks (LABs). Each macrocell has a programmable–AND/fixed–OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with shareable expander and high–speed parallel expander product terms to provide up to 32 product terms per macrocell. MAX 3000A devices provide programmable speed/power optimization. Speed–critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 3000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non–speed–critical signals are switching. The output drivers of all MAX 3000A devices can be set for 2.5 V or 3.3 V, and all input pins are 2.5–V, 3.3–V, and 5.0-V tolerant, allowing MAX 3000A devices to be used in mixed–voltage systems.

• High–performance, low–cost CMOS EEPROM–based programmabl logic devices (PLDs) built on a MAX architecture
• 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
• ISP circuitry compliant with IEEE Std. 1532
• Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
• Enhanced ISP features:
  • Enhanced ISP algorithm for faster programming
  • ISP_Done bit to ensure complete programming
  • Pull-up resistor on I/O pins during in–system programming
• High–density PLDs ranging from 600 to 10,000 usable gates
• 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz
• MultiVolt I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels
• Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGA packages
• Hot–socketing support
• Programmable interconnect array (PIA) continuous routing structur for fast, predictable performance
• PCI compatible
• Bus–friendly architecture including programmable slew–rate control
• Open–drain output option
• Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
• Programmable power–saving mode for a power reduction of over 50% in each macrocell
• Configurable expander product–term distribution, allowing up to 32 product terms per macrocell
• Programmable security bit for protection of proprietary designs
• Enhanced architectural features, including:
  • 6 or 10 pin- or logic–driven output enable signals
  • Two global clock signals with optional inversion
  • Enhanced interconnect resources for improved routability
  • Programmable output slew–rate control
• Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations
• Additional design entry and simulation support provided by EDIF 200 and 300 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
• Programming support with the Altera master programming unit (MPU), MasterBlaster communications cable, ByteBlasterMV parallel port download cable, BitBlaster serial download cable as well as programming hardware from third–party manufacturers and any in–circuit tester that supports Jam Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf)