LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
Cart
TI 74AC16244DGGR product image
  • 74AC16244DGGR thumbnail 1
  • 74AC16244DGGR thumbnail 2
  • 74AC16244DGGR thumbnail 3
  • Pinout
  • Footprint
Images for reference only

TI 74AC16244DGGRRoHS

Manufacturer
TI
MPN
74AC16244DGGR
LCSC Part #
C2675931
Packaging
TSSOP-48-6.1mm
Customer #
Key Attributes
16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS
Datasheetpdf iconTI 74AC16244DGGR
In-Stock: 6
6 In stock, ships now
Minimum: 1Multiple: 1Sales Unit: Piece
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 2.2509$ 2.25
10+$ 1.8918$ 18.92
30+$ 1.6678$ 50.03
100+$ 1.4377$ 143.77
500+$ 1.3334$ 666.70
1,000+$ 1.2889$ 1288.90
Standard Packaging2000/Full Reel
Better price for more quantity?
$

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers
ManufacturerTI
PackagingTSSOP-48-6.1mm
Input type-
Current - Output High(IOH)24mA
Series74AC
Voltage - Supply3V~5.5V
Output TypeTri-State
Current - Output Low(IOL)24mA
Number of Bits per Element4
Channel TypeUnidirectional
FeaturesOutput enable
Number of Elements4
Propagation Delay4.6ns@5V,50pF
Quiescent Current80uA
Report an ErrorShow similar products (0) >

Introduction

AI Translation

The ’AC16244 are 16-bit buffers/line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. They can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical active-low output-enable (OE) inputs. When OC(overline) is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. The 74AC16244 is packaged in the TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

Features

AI Translation
  • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed Vcc and GND Configuration Minimizes High-Speed Switching Noise
  • EPIC (Enhanced-Performance Implanted CMOS) 1- II' [μm] Process
  • 500 - mA Typical Latch-Up Immunity at 125℃
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages Using 25-mil Center-to-Center Pin Spacings, and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings