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TI SN74LS175DR
| Manufacturer | |
| MPN | SN74LS175DR |
| LCSC Part # | C7745 |
| Packaging | SOIC-16 |
| Customer # | |
| Key Attributes | HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR |
| Datasheet |  TI SN74LS175DR |
| RoHS Compliance | 2 documents available |
| Alternative Parts | 10 |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | SOIC-16 | |
| Voltage - Supply | 4.75V~5.25V | |
| Number of Bits per Element | 4 | |
| Output Type | Complementary type | |
| Operating Temperature | 0℃~+70℃ | |
| Series | 74LS Series | |
| Synchronous/Asynchronous | Asynchronous | |
| Number of Elements | 1 | |
| Current - Output High(IOH) | 400uA | |
| Current - Output Low(IOL) | 8mA | |
| Setup Time | 20ns | |
| Quiescent Current | 18mA | |
| Hold Time | 5ns | |
| Propagation Delay | 25ns@5V,15pF | |
| Trigger Type | Rising Edge |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | SOIC-16 | |
| Voltage - Supply | 4.75V~5.25V | |
| Number of Bits per Element | 4 | |
| Output Type | Complementary type | |
| Operating Temperature | 0℃~+70℃ | |
| Series | 74LS Series | |
| Synchronous/Asynchronous | Asynchronous |
| Type | Description | |
|---|---|---|
| Number of Elements | 1 | |
| Current - Output High(IOH) | 400uA | |
| Current - Output Low(IOL) | 8mA | |
| Setup Time | 20ns | |
| Quiescent Current | 18mA | |
| Hold Time | 5ns | |
| Propagation Delay | 25ns@5V,15pF | |
| Trigger Type | Rising Edge |
Introduction
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits.
Applications
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.5697 | $ 0.57 |
| 10+ | $ 0.5583 | $ 5.58 |
| 30+ | $ 0.5501 | $ 16.50 |
| 100+ | $ 0.542 | $ 54.20 |
Standard Packaging2500/Full Reel | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | SOIC-16 | |
| Voltage - Supply | 4.75V~5.25V | |
| Number of Bits per Element | 4 | |
| Output Type | Complementary type | |
| Operating Temperature | 0℃~+70℃ | |
| Series | 74LS Series | |
| Synchronous/Asynchronous | Asynchronous | |
| Number of Elements | 1 | |
| Current - Output High(IOH) | 400uA | |
| Current - Output Low(IOL) | 8mA | |
| Setup Time | 20ns | |
| Quiescent Current | 18mA | |
| Hold Time | 5ns | |
| Propagation Delay | 25ns@5V,15pF | |
| Trigger Type | Rising Edge |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | SOIC-16 | |
| Voltage - Supply | 4.75V~5.25V | |
| Number of Bits per Element | 4 | |
| Output Type | Complementary type | |
| Operating Temperature | 0℃~+70℃ | |
| Series | 74LS Series | |
| Synchronous/Asynchronous | Asynchronous |
| Type | Description | |
|---|---|---|
| Number of Elements | 1 | |
| Current - Output High(IOH) | 400uA | |
| Current - Output Low(IOL) | 8mA | |
| Setup Time | 20ns | |
| Quiescent Current | 18mA | |
| Hold Time | 5ns | |
| Propagation Delay | 25ns@5V,15pF | |
| Trigger Type | Rising Edge |
Introduction
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits.
Applications
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators
C7745 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
Alternative Parts
| MPN | Manufacturer | Packaging | Availability | Unit Price | ||
|---|---|---|---|---|---|---|
| CD74HCT175M96 | TI | SOIC-16 | 800 | $ 0.3384 | ||
| CD40175BM(LX) | lingxingic | SOP-16 | 265 | $ 0.3174 | ||
| CD74HC175M96 | TI | SOIC-16 | 90 | $ 0.8176 | ||
| HEF40175BT,653 | Nexperia | SO-16 | 4 | $ 1.1233 | ||
| CD74ACT175M96 | TI | SOIC-16 | 2 | $ 1.6553 | ||
| 74HCT175D-Q100J | Nexperia | SOP-16 | 0 | $ 0.3343 | ||
| CD74HCT175MR2499 | TI | SOIC-16 | 0 | $ 0.0976 | ||
| 74HCT175D,653 | Nexperia | SOP-16 | 0 | $ 0.6221 | ||
| HEF40175BT,652 | Nexperia | SO-16 | 0 | $ 0.2252 | ||
| MM74HC175MX | onsemi | SOIC-16 | 0 | $ 0.2765 |