RENESAS 89H64H16AG2ZCBLGI

Utilizing standard PCI Express interconnect, the PES64H16AG2 provides the most efficient fan-out solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 64 GBps (512 Gbps) of aggregated, full-duplex switching capacity through 64 integrated serial lanes, using proven and robust technology. Each lane provides 5 GT/s of bandwidth in both directions and is fully compliant with PCI Express Base Specification, Revision 2.0. The PES64H16AG2 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 2.0. The PES64H16AG2 can operate either as a store and forward or cut-through switch. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded processors with limited connectivity. The PES64H16AG2 is a partitionable PCIe switch. This means that in addition to operating as a standard PCI express switch, the PES64H16AG2 ports may be partitioned into groups that logically operate as completely independent PCIe switches.

• 64-lane 16-port PCIe switch
• Eight x8 switch ports each of which can bifurcate to two x4 ports (total of sixteen x4 ports)
• Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Gen1 operation
• Delivers up to 64 GBps (512 Gbps) of switching capacity
• Supports 128 Bytes to 2 KB maximum payload size
• Low latency cut-through architecture
• Supports one virtual channel and eight traffic classes
• PCI Express Base Specification 2.0 compliant
• Implements the following optional PCI Express features:
  • Advanced Error Reporting (AER) on all ports
  • End-to-End CRC (ECRC)
  • Access Control Services (ACS)
  • Power Budgeting Enhanced Capability
  • Device Serial Number Enhanced Capability
  • Sub-System ID and Sub-System Vendor ID Capability
  • Internal Error Reporting ECN
  • Multicast ECN
  • VGA and ISA enable
  • L0s and L1 ASPM
  • ARI ECN
• x4 and x8 ports
• Ability to merge adjacent x4 ports to create a x8 port
• Automatic per port link width negotiation (x8→x4→x2→x1)
• Crosslink support
• Automatic lane reversal
• Autonomous and software managed link width and speed control
• Per lane SerDes configuration
• IDT proprietary feature that creates logically independent switches in the device
• Supports up to 16 fully independent switch partitions
• Configurable downstream port device numbering
• Supports dynamic reconfiguration of switch partitions
  • Dynamic port reconfiguration — downstream, upstream
  • Dynamic migration of ports between partitions
  • Movable upstream port within and between switch partitions
• Supports Root (BIOS, OS, or driver), Serial EEPROM, or SMBus switch initialization
• Common switch configurations are supported with pin strapping (no external components)
• Supports in-system Serial EEPROM initialization/programming
• Port arbitration: Round robin
• Request metering: IDT proprietary feature that balances bandwidth among switch ports for maximum system throughput
• High performance switch core architecture: Combined Input Output Queued (CIOQ) switch architecture with large buffers
• Compliant to the PCI-SIG multicast ECN
• Supports arbitrary multicasting of Posted transactions
• Supports 64 multicast groups
• Multicast overlay mechanism support
• ECRC regeneration support
• Supports 100 MHz and 125 MHz reference clock frequencies
• Flexible port clocking modes:
  • Common clock
  • Non-common clock
  • Local port clock with SSC and port reference clock input
• Hot-plug controller on all ports
• Hot-plug supported on all downstream switch ports
• All ports support hot-plug using low-cost external I2C I/O expanders
• Direct package pin support for hot-plug on 5 ports
• Configurable presence detect supports card and cable applications
• GPE output pin for hot-plug event notification
• Enables SCI/SMI generation for legacy operating system support
• Hot-swap capable I/O
• Supports D0, D3hot and D3 power management states
• Active State Power Management (ASPM):
  • Supports L0, L0s, L1, L2/L3 Ready and L3 link states
  • Configurable L0s and L1 entry timers allow performance/power-savings tuning
• Supports PCI Express Power Budgeting Capability
• SerDes power savings:
  • Supports low swing / half-swing SerDes operation
  • SerDes optionally turned-off in D3hot
  • SerDes associated with unused ports are turned-off
  • SerDes associated with unused lanes are placed in a low power state
• ECRC support
• AER on all ports
• SECDED ECC protection on all internal RAMs
• End-to-end data path parity protection
• Checksum Serial EEPROM content protected
• Autonomous link reliability (preserves system operation in the presence of faulty links)
• Ability to generate an interrupt (INTx or MSI) on link up/down transitions

• servers
• storage
• communications
• embedded systems
• multi-host or intelligent I/O based systems with inter-domain communication