WCH CH559L

The CH559 is an enhanced E8051 MCU compatible with MCS51 instruction set. 79% of its instructions are single- byte single- cycle instructions, and the average instruction speed is 8 to 15 times faster than that of the standard MCS51. CH559 supports up to 56MHz system clock, built- in 64KB Flash- ROM, 256B on- chip iRAM, 6KB on- chip xRAM, and some of xRAM support DMA mode. CH559 has a built- in ADC converter, 4 timers/PWM, 2 UARTs, 2SPIs, and dual port Root- HUB, which support USB- Host and USB- Device modes.

• Core: Enhanced E8051 core, compatible with MCS51 instruction set, 79% of its instructions are single- byte single- cycle instructions, and the average instruction speed is 8 to 15 times faster than that of the standard MCS51, with special XRAM data fast copy instruction, and dual DPTR pointer.
• ROM: Non- volatile 64KB Flash- ROM, which supports 100K writing cycles, it can be all used for program memory. Or it can be divided into three pieces, 60KB for program memory, 1KB for data- flash and 3KB for BootLoader or ISP code.
• RAM: 256- byte on- chip iRAM, for fast data cache or stack pointer; 6KB on- chip xRAM, for mass data or DMA operation; support off- chip SRAM extending up to 32KB.
• USB: Built- in USB controller and dual USB transceiver, supports USB- Host and USB- Device modes, supports USB 2.0 full speed (12Mbps) and low speed (1.5Mbps). In USB- Host mode, CH559 may manage 2 USB devices at the same time. Maximum support 64- byte packet, built- in FIFO and support DMA mode.
• Timer: 4 timers. T0, T1 and T2 are standard MCS51 timers, T2 is extended to support 2 captures. TMR3 is built in 8- level FIFO, support DMA and signal capturing and 16- bit PWM output.
• PWM: 3 PWM outputs. PWM1 and PWM2 are 2 8- bit PWM outputs, TMR3 supports 16- bit PWM output.
• UART: 2 UARTs. UART0 is a standard MCS51 UART. UART1 is compatible with 16C550, built- in 8- level FIFO, supports Modem signals, supports RS485 half- duplex mode, and supports local address presetting for auto- matching or multi- device communication.
• SPI: 2 SPIs, high speed rate up to Fsys/2, support simplex multiplexing of serial data input and output. SPI0 has built- in FIFO, supports Master/Slave mode. SPI1 only supports Master mode.
• ADC: 8- channel 10- bit or 11- bit A/D converter, built- in 2- level FIFO, supports DMA, sampling rate up to 1Mbps, and support 2 channels auto- switching detection.
• LED- CTRL: LED control card interface, built- in 4- level FIFO, supports DMA mode, and 1/2/4- channel data interface, high speed rate up to Fsys/2.
• XBUS: 8- bit parallel external bus, compatible with standard MCS51 bus, used to connect off- chip SRAM memory or other peripherals, supports direct 15- bit address or ALE multiplexed low 8- bit address, and supports 4 bus speeds.
• GPIO: Supports up to 45 GPIO pins (including XI/XO, RST and USB signal pins), 3.3V voltage output, and all support 5V- tolerant input except P1.0- P1.7, XI, XO or RST.
• Interrupt: Supports 14 interrupt sources, including 6 interrupts compatible with the standard MCS51 (INT0, T0, INT1, T1, UART0, T2), and 8 extended interrupts (SPI0, TMR3, USB, ADC, UART1, PWM1, GPIO, WDOG). GPIO interrupt can be selected from 7 pins.
• Watch- Dog: 8- bit configure presetting watchdog timer WDOG, support timer interrupt.
• Reset: Supports 4 reset sources, built- in power on reset, supports software reset and watchdog overflow reset, configurable external input reset.
• Clock: Built- in 12MHz clock, support external crystal oscillator through alternate GPIO pins, built- in PLL for USB clock and Fsys.
• Power: Built- in 5V to 3.3V LDO, 3.3V working voltage internal, support 3.3V and 5V voltage input. Support low power sleep mode, support USB, UART0, UART1, SPI0 and some GPIOs wake- up.
• Unique ID for identification.