Infineon/CYPRESS S29AL016J70TFI020

The S29AL016J is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball Fine-pitch BGA (0.8 mm pitch), 64-ball Fortified BGA (1.0 mm pitch) and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 VPP or 5.0 VCC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers. The device offers access time of 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The S29AL016J is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device.

• Architecture Advantages:
  • Single power supply operation, full voltage range: 2.7 to 3.6V, read/write operations for battery-powered applications
  • Manufactured using 110 nm process technology, fully compatible with 200 nm S29AL016D
  • Secured Silicon Sector region, 128-word/256-byte sector, permanent and secure identification via 8-word/16-byte random electronic serial number, accessible via command sequence, programmable and lockable at factory or by customer
  • Flexible sector architecture: one 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte sectors in byte mode; one 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32 Kword sectors in word mode
  • Sector group protection, hardware method to lock sectors preventing any program or erase operations within the sector, sectors lockable in-system or via programming equipment, temporary sector unlock feature allows code changes in previously locked sectors
  • Unlock Bypass program command reduces overall programming time when issuing multiple program command sequences
  • Top or bottom boot block configuration available
  • JEDEC standard compatible, pin and software compatible with single-supply flash memory, with superior inadvertent write protection
• Performance Characteristics:
  • High performance, access time as fast as 55 ns, for automotive (AEC-Q100 Grade 3, -40°C to +85°C; AEC-Q100 Grade 1, -40°C to +125°C), industrial temperature range (-40°C to +85°C), and extended temperature range (-40°C to +125°C)
  • Ultra-low power consumption (typical at 5 MHz): auto sleep mode current 0.2 μA, standby mode current 0.2 μA, read current 7 mA, program/erase current 20 mA
  • Endurance: typical 1,000,000 cycles per sector
  • Data retention: typical 20 years
• Software Features:
  • CFI (Common Flash Interface) compliant, provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices
  • Erase Suspend/Erase Resume, suspends erase operation to read data from or program data to non-erasing sectors, then resumes erase operation
  • Data# Polling and Toggle Bit, software method for detecting completion of program or erase operations
• Hardware Features:
  • Ready/Busy# pin (RY/BY#), hardware method for detecting completion of program or erase cycle
  • Hardware reset pin (RESET#), hardware method to reset the device to read array data state
  • WP# input pin, for boot sector devices, when at VIL, protects the first or last 16 Kbyte sector according to boot configuration (top boot or bottom boot)