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Infineon/CYPRESS CY62187EV30LL-55BAXI product image
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Infineon/CYPRESS CY62187EV30LL-55BAXIRoHS

Manufacturer
MPN
CY62187EV30LL-55BAXI
LCSC Part #
C914894
Packaging
FBGA-48
Customer #
Key Attributes
64Mbit 2.2V~3.6V Parallel Port (Parallel) FBGA-48 Memory RoHS
Datasheetpdf iconInfineon/CYPRESS CY62187EV30LL-55BAXI
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QtyUnit Price(Reference Only)Total Amount
1+$ 24.2714$ 24.27
10+$ 22.6109$ 226.11
Standard Packaging210/Full Tray
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory
ManufacturerInfineon/CYPRESS
PackagingFBGA-48
Operating Temperature-40℃~+85℃
FeaturesAuto power-down function
Memory Size64Mbit
Voltage - Supply2.2V~3.6V
Access Time55ns
Current - Supply38mA
Standby Supply Current8uA
InterfaceParallel Port (Parallel)

Introduction

AI Translation

CY62187EV30 is a high-performance CMOS static RAM organized as 4M words by 16 bits. This device features an advanced circuit design to provide ultra-low active current. It is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular phones. The device also has an Automatic Power Down feature that significantly reduces power consumption by 99 percent when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a High-Z state when: deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins A0 through A21. If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins A0 through A21. To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. If BLE is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If BHE is LOW, then data from the memory appears on I/O8 to I/O15.

Features

AI Translation
  • Very high speed: 55 ns
  • Wide voltage range: 2.2 V to 3.6 V
  • Ultra-low standby power:
    • Typical standby current: 8 μA
    • Maximum standby current: 48 μA
  • Ultra-low active power: Typical active current: 15 mA at f = 1 MHz
  • Easy memory expansion with CE1, CE2, and OE features
  • Automatic Power Down when deselected
  • CMOS for optimum speed and power
  • Available in Pb-free 48-ball FBGA package