TI SN74LS161ANSR
| Manufacturer | |
| MPN | SN74LS161ANSR |
| LCSC Part # | C7741 |
| Packaging | SOIC-16-208mil |
| Customer # | |
| Key Attributes | Synchronous 4-Bit Counters |
| Datasheet |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Manufacturer | TI | |
| Packaging | SOIC-16-208mil | |
| Logic Family | 74LS | |
| Voltage - Supply | 4.75V | |
| Direction | - | |
| Trigger Type | Rising Edge | |
| Timing | Synchronous | |
| Operating Temperature | 0℃~+70℃ | |
| Reset | Asynchronous | |
| Number of Elements | 1 | |
| Propagation Delay | 24ns | |
| Count Rate | 25MHz | |
| Features | Synchronous counting;Programmable divide ratio;Cascade counter;Reset function |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Manufacturer | TI | |
| Packaging | SOIC-16-208mil | |
| Logic Family | 74LS | |
| Voltage - Supply | 4.75V | |
| Direction | - | |
| Trigger Type | Rising Edge |
| Type | Description | |
|---|---|---|
| Timing | Synchronous | |
| Operating Temperature | 0℃~+70℃ | |
| Reset | Asynchronous | |
| Number of Elements | 1 | |
| Propagation Delay | 24ns | |
| Count Rate | 25MHz | |
| Features | Synchronous counting;Programmable divide ratio;Cascade counter;Reset function |
Introduction
These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition.
Features
- Internal Look-Ahead for Fast Counting
- Carry Output for n-Bit Cascading
- Synchronous Counting
- Synchronously Programmable
- Load Control Line
- Diode-Clamped Inputs
- The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating
- 'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clock circuit. Changes at control inputs (enable P or T, or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times.
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 1.7593 | $ 1.76 |
| 10+ | $ 1.5498 | $ 15.50 |
| 30+ | $ 1.401 | $ 42.03 |
| 100+ | $ 1.2667 | $ 126.67 |
| 500+ | $ 1.2043 | $ 602.15 |
| 1,000+ | $ 1.1787 | $ 1178.70 |
Standard Packaging2000/Full Reel | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Manufacturer | TI | |
| Packaging | SOIC-16-208mil | |
| Logic Family | 74LS | |
| Voltage - Supply | 4.75V | |
| Direction | - | |
| Trigger Type | Rising Edge | |
| Timing | Synchronous | |
| Operating Temperature | 0℃~+70℃ | |
| Reset | Asynchronous | |
| Number of Elements | 1 | |
| Propagation Delay | 24ns | |
| Count Rate | 25MHz | |
| Features | Synchronous counting;Programmable divide ratio;Cascade counter;Reset function |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Manufacturer | TI | |
| Packaging | SOIC-16-208mil | |
| Logic Family | 74LS | |
| Voltage - Supply | 4.75V | |
| Direction | - | |
| Trigger Type | Rising Edge |
| Type | Description | |
|---|---|---|
| Timing | Synchronous | |
| Operating Temperature | 0℃~+70℃ | |
| Reset | Asynchronous | |
| Number of Elements | 1 | |
| Propagation Delay | 24ns | |
| Count Rate | 25MHz | |
| Features | Synchronous counting;Programmable divide ratio;Cascade counter;Reset function |
Introduction
These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition.
Features
- Internal Look-Ahead for Fast Counting
- Carry Output for n-Bit Cascading
- Synchronous Counting
- Synchronously Programmable
- Load Control Line
- Diode-Clamped Inputs
- The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating
- 'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clock circuit. Changes at control inputs (enable P or T, or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times.
C7741 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



