Alliance Memory AS4C256M16D3LC-10BANTR

The 4Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 4Gb chip is organized as 32Mbit x 16 x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous fashion. The DDR3L SDRAM is a high-speed dynamic random access memory internally configured as an eight-bank DRAM. The DDR3L SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n Prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3L SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR3L SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be activated (BA0 - BA2 select the bank; A0 - A14 select the row). The address bit registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register.

• JEDEC Standard Compliant
• AEC-Q100 Compliant
• Power supplies: VΔD ≅ VDDQ = +1.35V
• Backward compatible to VDD & VDDQ = +1.5V ± 0.075V
• Operating temperature: TC = -40 ~ 105℃ (Automotive)
• Supports JEDEC clock jitter specification
• Fully synchronous operation
• Fast clock rate: 800/933MHz
• Differential Clock, CK & CK#
• Bidirectional differential data strobe - DQS & DQS#
• 8 internal banks for concurrent operation
• 8n-bit prefetch architecture
• Pipelined internal architecture
• Precharge & active power down
• Programmable Mode & Extended Mode registers
• Additive Latency (AL): 0, CL - 1, CL - 2
• Programmable Burst lengths: 4, 8
• Burst type: Sequential / Interleave
• Output Driver Impedance Control
• Auto Refresh and Self Refresh - Not Support self refresh function with TC > 95℃
• Average refresh period - 8192 cycles/64ms (7.8us at -40℃ ≤ Tc ≤ +85℃); 8192 cycles/32ms (3.9us at +85℃ ≤ Tc ≤ +95℃); 8192 cycles/16ms (1.95us at +95℃ ≤ Tc ≤ +105℃)
• Write Leveling
• ZQ Calibration
• Dynamic ODT (Rtt_Nom & Rtt_WR)
• RoHS compliant
• 96 - ball 7.5 x 13.5 x 1.2mm FBGA package - Pb and Halogen Free