Hangzhou Ruimeng Tech MS3494

MS3494 contains an 8×16 analog switch array, a 7-to-128 address decoder, and latch circuitry. By applying different address signals, all 128 switches can be individually addressed. A logic "1" or "0" applied to the DATA port will turn the corresponding analog switch on or off. The analog signal range extends from VDD to VEE. The CS pin also allows expansion of the chip's switch array.

The MS3494 is an 8×16 analog switch matrix circuit. The switch matrix consists of 8 columns in the Y direction and 16 rows in the X direction. When a switch is open, complete isolation is achieved between the corresponding X row and Y column; when a switch is closed, the X row and Y column are connected.

The control register consists of a 128-bit writable RAM, with individual bits selected via address input lines (AX0–AX3, AY0–AY2). Data is written to memory through the DATA port. When both STROBE and CS are high, data can be written to the DATA port; data is latched on the falling edge of STROBE. To ensure a valid write, the DATA port must be held stable prior to the falling edge. Writing a logic "1" to a memory cell closes the corresponding crosspoint switch; writing a logic "0" opens it. When data is written to memory, only the state of the addressed crosspoint changes — all other switches retain their current states. Different X and Y combinations can be achieved by writing different data to the controller. When RESET is asserted logic "1", all switches are turned off and all memory data is cleared, regardless of the state of CS. Two voltage reference pins (VSS and VEE) support negative analog signals. The digital signal voltage range is from VDD to VSS, and the analog signal voltage range is from VDD to VEE. If only a single supply is used, VSS and VEE may be connected together.

Under the control of the STROBE and CS enable signals, 7 address lines feed into the 7-to-128 address decoder. DATA is buffered and applied as the input to all memory cells. Data and address information can be written to the latch only when RESET is low and CS is high; data is latched on the falling edge of STROBE. Data may only be written while STROBE is high, during which switches can be turned on or off. To ensure a valid write, data must be held stable before the falling edge of STROBE.

• Integrated control latch and address decoding
• Very short setup and hold times
• Wide voltage range: 4.5V~13.2V
• 12Vₚ₋ₚ analog signal
• RON max 65Ω (VDD = 12V, 25℃)
• RON ≤10Ω @VDD = 12V, 25℃
• Low distortion, full CMOS switch
• Low feedthrough and crosstalk
• Independent analog and digital reference voltage supply
• PLCC44

• Key systems
• PBX systems
• Analog/digital multiplexers
• Audio/video switches
• Mobile device test equipment