TI SN74LVTH125PWR

These bus buffers are designed specifically for low-voltage (3.3 - V) VCC operation, but with the capability to provide a TTL interface to a 5 - V system environment. The 'LVTH125 devices feature independent line drivers with 3 - state outputs. Each output is in the high - impedance state when the associated output - enable (OE(overline)) input is high. Active bus - hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus - hold circuitry is not recommended. When VCC is between 0 and 1.5V, the devices are in the high - impedance state during power up or power down. However, to ensure the high - impedance state above 1.5V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current - sinking capability of the driver. These devices are fully specified for hot - insertion applications using Ioff and power - up 3 - state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power - up 3 - state circuitry places the outputs in the high - impedance state during power up and power down, which prevents driver conflict.

• Support Mixed - Mode Signal Operation (5 - V Input and Output Voltages With 3.3 - V Vcc)
• Support Unregulated Battery Operation Down to 2.7V
• Typical VOLb (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25℃
• Ioff and Power - Up 3 - State
• Support Hot Insertion
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch - Up Performance Exceeds 500 mA Per JESD 17
• ESD Protection Exceeds JESD 22 2000 - V Human - Body Model (A114 - A) 200 - V Machine Model (A115 - A)