Lattice LC4064ZE-5TN48I

The high-performance ispMACH 4000ZE series offers an ultra-low-power CPLD solution. This new series is based on the industry-leading ispMACH 4000 architecture. While retaining the advantages of the previous generation of products, the ispMACH 4000ZE architecture focuses on significant innovations, combining high performance with low power consumption to create a flexible CPLD series. For example, the new Power Guard feature of this series can prevent internal logic flipping caused by unnecessary I/O pin activities, thereby minimizing dynamic power consumption. The ispMACH 4000ZE combines high speed, low power consumption, and the flexibility required for easy design. With its powerful global routing pool and output routing pool, products in this series have a high first-time layout success rate, good timing predictability, strong routing capabilities, excellent pin output retention, and convenient density migration. The macrocell density of the ispMACH 4000ZE series ranges from 32 to 256. In Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA), and Ultra Chip Scale BGA (ucBGA) packages, there are a variety of density - I/O combinations to choose from, with the number of pins/bonding balls ranging from 32 to 144. The device includes a user-programmable internal oscillator and a timer, which can be used for housekeeping-type state machine tasks such as LED control and keyboard scanners. This feature can be optionally disabled to save power. The ispMACH 4000ZE series has enhanced system integration capabilities. It supports a 1.8V power supply voltage and interface voltages of 3.3V, 2.5V, 1.8V, and 1.5V. In addition, when the I/O group is configured to operate at 3.3V, the input can be safely driven to 5.5V, making the products in this series 5V tolerant. The ispMACH 4000ZE also provides enhanced I/O features, such as slew rate control, PCI compatibility, bus hold latches, pull-up resistors, pull-down resistors, open-drain outputs, and hot-swap functionality. The pull-up, pull-down, and bus hold functions can be controlled on a "per-pin" basis. Products in the ispMACH 4000ZE series can be programmed in-system at 1.8V through the IEEE Standard 1532 interface. The IEEE Standard 1149.1 boundary scan test function also allows product testing on automated test equipment. The 1532 interface signals TCK, TMS, TDI, and TDO are referenced to VCC (logic core).

• fMAX = 260MHz maximum operating frequency
• tpD = 4.4 ns propagation delay
• Up to four global clock pins with programmable clock polarity control
• Up to 80 product terms per output
• Flexible CPLD macrocells with independent clock, reset, preset, and clock enable control
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent first-time fit and re-fit capability
• Wide input steering (36-input logic block) for fast counters, state machines, and address decoders
• Typical standby current as low as 10μA
• 1.8V core; low dynamic power consumption
• Operates down to 1.6V VCC
• Ideal solution for power-sensitive consumer applications
• Per-pin pull-up, pull-down, or bus-hold control
• Power Guard with multiple enable signals
• 32 to 256 macrocells
• Multiple temperature range support – Commercial: junction temperature (Tj) 0 to 90℃ – Industrial: junction temperature (Tj) -40 to 105℃
• Space-saving ucBGA and csBGA packages
• Compatible with 3.3V, 2.5V, 1.8V, or 1.5V LVCMOS I/O interfaces
• 5V-tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
• Hot-pluggable support
• Optional open-drain output
• Programmable output slew rate
• 3.3V PCI compatible
• Fast setup path on I/O pins
• Input hysteresis
• 1.8V core power supply
• IEEE 1149.1 boundary scan test support
• Compliant with IEEE 1532 in-system configuration (ISC) standard
• 1.8V in-system programming (ISP) via boundary scan TAP
• Lead-free package options available
• On-chip user oscillator and timer