RENESAS 71V67603S166PF8

The IDT71V67603/7803 are high-speed SRAMs organized as 256K x 36/512K x 18. These memories contain write, data, address, and control registers. Internal logic allows the memory to generate self-timed writes based on a decision that can be deferred until the end of the write cycle. An internal burst address counter accepts the first-cycle address from the processor and initiates the access sequence. The first cycle of output data is pipelined one cycle prior to the next rising clock edge. If burst mode operation is selected (ADV = Low), the output data for the subsequent three cycles will be available to the user on the next three rising clock edges. The sequence of these three addresses is defined by the internal burst counter and the LBO input pin. The IDT71V67603/7803 SRAMs are fabricated in a high-performance CMOS process and are packaged in JEDEC standard 14mm x 20mm 100-pin TQFP, 119-ball BGA, and 165-ball FBGA packages.

• Memory configurations: 256K x 36, 512K x 18
• High system speed support: 166MHz 3.5ns clock access time, 150MHz 3.8ns clock access time, 133MHz 4.2ns clock access time
• LBO input selectable interleaved or linear burst mode
• Self-timed write cycle with global write control, byte write enable, and byte write
• 3.3V core power supply
• Power-down control via ZZ input
• 3.3V I/O power supply
• Available in JEDEC standard 100-pin TQFP, 119-ball BGA, and 165-ball FBGA packages