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ADI ADSP-SC584KBCZ-4A

Manufacturer
MPN
ADSP-SC584KBCZ-4A
LCSC Part #
C660016
Packaging
BGA-349
Customer #
Key Attributes
BGA-349 DSP (Digital Signal Processors) RoHS
Datasheetpdf iconADI ADSP-SC584KBCZ-4A
RoHS Compliance1 documents available
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1+$ 18.3$ 18.30
10+$ 17.4244$ 174.24
30+$ 15.9089$ 477.27
100+$ 14.5861$ 1458.61
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/DSP (Digital Signal Processors)
ManufacturerADI
PackagingBGA-349

Introduction

AI Translation

The ADSP-SC58x/ADSP-2158x processors are members of the SHARC family of products. The ADSP-SC58x processor is based on the SHARC+ dual core and the Arm Cortex-A5 core. The ADSP-SC58x/ADSP-2158x SHARC processors are members of the SIMD SHARC family of digital signal processors (DSPs) that feature Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large, on-chip, static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a set of industry leading system peripherals and memory, the Arm Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

Features

AI Translation
  • Dual enhanced SHARC+ high performance floating-point cores
  • Up to 500 MHz per SHARC+ core
  • Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core with parity (optional ability to configure as cache)
  • 32-bit, 40-bit, and 64-bit floating-point support
  • 32-bit fixed point
  • Byte, short-word, word, long-word addressed
  • Arm Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle
  • 32 kB L1 instruction cache/32 kB L1 data cache
  • 256 kB Level 2 (L2) cache with parity
  • Powerful DMA system
  • On-chip memory protection
  • Integrated safety features
  • Large on-chip L2 SRAM with ECC protection, up to 256 kB
  • On-chip L2 ROM (512 kB)
  • Two Level 3 (L3) interfaces optimized for low system power, providing a 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices
  • Security and Protection Cryptographic hardware accelerators
  • Fast secure boot with IP protection
  • Support for Arm TrustZone
  • Accelerators High performance pipelined FFT/IFFT engine
  • FIR, IIR, HAE, SINC offload engines
  • AEC-Q100 qualified for automotive applications

Applications

AI Translation
  • automotive
  • professional audio
  • industrial-based applications