ADI ADSP-21371BSWZ-2B

High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory, ADSP-21371—1M bits of on-chip SRAM and 4M bits of on-chip mask-programmable ROM On-chip memory, ADSP-21375—0.5M bits of on-chip SRAM and 2M bits of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21371/ADSP-21375 processors are available with a 200/266 MHz core instruction rate with unique audiocentric peripherals such as the digital applications interface, S/PDIF transceiver, serial ports, precision clock generators, and more.

The ADSP-21371/ADSP-21375 SHARC processors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The processors are 32-bit/40-bit floating-point processors optimized for high performance automotive audio applications with their large on-chip SRAM and mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI).

As shown in the functional block diagram on Page 1, the processors use two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the processors achieve an instruction cycle time of 3.75 ns at 266 MHz. With its SIMD computational hardware, the processors can perform 1.596 GFLOPS running at 266 MHz.

• ADSP-21371—S/PDIF-compatible digital audio receiver/transmitter
• ADSP-21371—8 dual data line serial ports that operate at up to 33 Mbps on each data line — each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair
• 16 PWM outputs configured as four groups of four outputs
• ROM-based security features include JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code
• PLL has a wide variety of software and hardware multiplier/divider ratios
• Available in a 208-lead LQFP_EP package
• Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle
• One periodic interval timer with pinout
• On-chip SRAM (1M bit, ADSP-21371; 0.5M bit, ADSP-21375)
• On-chip mask-programmable ROM (4M bit, ADSP-21371; 2M bit, ADSP-21375)