MICROCHIP M7AFS600-1FGG484

Actel Fusion mixed-signal FPGAs meet system architects' needs for simplified design and unleashed creativity. As the world's first mixed-signal programmable logic family, Fusion integrates mixed-signal analog, flash memory, and FPGA architecture into a single monolithic device. This technology leverages the unique properties of flash-based FPGAs — including high-isolation triple-well process and support for high-voltage transistors — to meet the stringent demands of mixed-signal system design. It opens new possibilities for system development, enabling designers to integrate a wide range of functions into a single device while providing the flexibility to upgrade late in the manufacturing process or after field deployment. The device offers an excellent alternative to costly and time-consuming mixed-signal ASIC design.

• Advanced 130 nm, 7-layer metal, Flash-based CMOS process
• Non-volatile: program retained at power-off
• Single-chip solution, ready at power-up
• 350 MHz system performance
• User Flash: 2 Mbits to 8 Mbits, configurable 8-bit, 16-bit, or 32-bit data path; 10 ns access time in pre-fetch mode
• Additional 1 kbit FlashROM
• Integrated ADC, up to 12-bit resolution, up to 600 ksps sample rate
• Internal 2.56 V or external reference voltage
• ADC supports up to 30 scalable analog input channels
• High-voltage input tolerance: –10.5 V to +12 V
• Current monitoring and temperature monitoring modules
• Up to 10 MOSFET gate driver outputs; supports P-channel and N-channel power MOSFETs; programmable drive strength: 1 µA, 3 µA, 10 µA, 30 µA, and 20 mA
• ADC accuracy better than 1%
• Integrated 100 MHz RC oscillator (1% accuracy)
• Crystal oscillator support (32 kHz to 20 MHz)
• Programmable real-time counter
• 6 clock conditioning circuits with 1 or 2 integrated PLLs; phase shift, frequency multiplication/division, and delay capability; input frequency 1.5~350 MHz, output frequency 0.75~350 MHz
• Single 3.3 V supply with integrated on-chip 1.5 V regulator
• Sleep and standby low-power modes
• Secure in-system programming via JTAG with 128-bit AES encryption
• FlashLock® technology for FPGA content protection
• Mixed-voltage operation: 1.5 V, 1.8 V, 2.5 V, and 3.3 V
• Per-bank I/O voltage selection, up to 5 banks per device
• Multiple single-ended and differential I/O standards
• Built-in I/O registers supporting 700 Mbps DDR operation
• Hot-swap I/O support
• Programmable output slew rate, drive strength, and weak pull-up/pull-down resistors
• Pin-compatible packages across the entire Fusion family
• Variable aspect ratio 4,608-bit SRAM blocks (×1, ×2, ×4, ×9, and ×18 configurations)
• True dual-port SRAM (except ×18 configuration)
• Programmable embedded FIFO control logic
• M7 and M1 Fusion devices support soft ARM7 core