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ADI AD9215BRUZ-65RoHS

Manufacturer
MPN
AD9215BRUZ-65
LCSC Part #
C653265
Packaging
TSSOP-28
Customer #
Key Attributes
10-Bit, 65/80/105 MSPS 3 V A/D Converter
Datasheetpdf iconADI AD9215BRUZ-65
In-Stock: 37
37 In stock, ships now
Minimum: 1Multiple: 1Sales Unit: Piece
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QtyUnit PriceTotal Amount
1+$ 17.2201$ 17.22
10+$ 17.0108$ 170.11
30+$ 16.6491$ 499.47
100+$ 16.3344$ 1633.44
Standard Packaging50/Full Tube
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC)
ManufacturerADI
PackagingTSSOP-28
Operating Temperature-40℃~+85℃
InterfaceParallel port
Quiescent Current (Iq)-
Voltage - Supply2.7V~3.3V
Number of Channels1
Integral non - linearity1.2LSB
Voltage ReferenceBuilt-in
Clock/OscillatorExternal
Clock Frequency65MHz
FeaturesInput buffer
Resolution(Bits)65MHz;10
S/N Ratio58dB
ADC architecturePipeline
Programmable GainNot supported

Introduction

AI Translation

The AD9215 is a family of monolithic, single 3V supply, 10-bit, 65/80/105 MSPS analog-to-digital converters (ADC). This family features a high performance sample-and-hold amplifier (SHA) and voltage reference. The AD9215 uses a multistage differential pipelined architecture with output error correction logic to provide 10-bit accuracy at 105 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential sample-and-hold amplifier (SHA) allows for a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9215 is suitable for applications in communications, imaging, and medical ultrasound. A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer compensates for wide variations in the clock duty cycle while maintaining excellent performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range signal indicates an overflow condition, which can be used with the MSB to determine low or high overflow.

Features

AI Translation
  • Single 3 V supply operation (2.7 V to 3.3 V)
  • SNR = 58 dBc (to Nyquist)
  • SFDR = 77 dBc (to Nyquist)
  • Low power ADC core: 96 mW at 65 MSPS, 104 mW @ 80 MSPS, 120 mW at 105 MSPS
  • Differential input with 300 MHz bandwidth
  • On-chip reference and sample-and-hold amplifier
  • DNL = ± 0.25 LSB
  • Flexible analog input: 1 V p-p to 2 V p-p range
  • Offset binary or twos complement data format
  • Clock duty cycle stabilizer

Applications

AI Translation
  • Ultrasound equipment
  • IF sampling in communications receivers
  • Battery-powered instruments
  • Hand-held scopemeters
  • Low cost digital oscilloscopes