ADI AD7928WBRUZ-REEL

The AD7908/AD7918/AD7928 are 8-bit, 10-bit, and 12-bit high speed, low power, 8-channel successive approximation ADCs, respectively. Operating from a single supply of 2.7 V to 5.25 V, they achieve throughput rates up to 1 MSPS. An on-chip low noise, wide bandwidth track-and-hold amplifier handles input frequencies in excess of 8 MHz. The conversion process and data acquisition are controlled via /CS and the serial clock signal, allowing easy interfacing to microprocessors or DSPs. The input signal is sampled on the falling edge of CS, at which point conversion is also initiated simultaneously. The devices feature no pipeline delay. The AD7908/AD7918/AD7928 use advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput, the AD7908/AD7918/AD7928 consume a maximum of 2 mA from a 3 V supply and 2.7 mA from a 5 V supply. By configuring the control register, the analog input range can be selected between 0 V to REF_IN or 0 V to 2×REF_IN, with standard binary or twos complement output coding available. The AD7908/AD7918/AD7928 feature 8 single-ended analog inputs with a channel sequencer, allowing the channel conversion sequence to be preprogrammed. The conversion time of the AD7908/AD7918/AD7928 depends on the SCLK frequency, which also serves as the master clock for conversion control.

• High throughput rate: 1 MSPS
• Rated voltage (AVDD): 2.7 V to 5.25 V
• Low power consumption: 6.0 mW (max, 1 MSPS, 3 V supply); 13.5 mW (max, 1 MSPS, 5 V supply)
• 8 (single-ended) inputs with sequencer
• Wide input bandwidth SINAD: 70 dB (min, 50 kHz input frequency, AD7928)
• Flexible power/serial clock speed management
• No pipeline delay high-speed serial interface: SPI/QSPI/MICROWIRE/DSP compatible
• Shutdown mode: 0.5 μA (max)
• 20-lead TSSOP package
• Automotive qualified
• High throughput rate, low power consumption. Throughput up to 1 MSPS; at maximum throughput with a 3 V supply, maximum power consumption is only 6 mW
• 8 single-ended inputs with channel sequencer. Channel order is user-selectable; the ADC cycles through conversions in the selected order
• Single-supply operation via V_DRIVE feature. With a 2.7 V to 5.25 V single supply, the V_DRIVE feature allows the serial interface to connect directly to a 3 V or 5 V processor system independent of AVDD
• Flexible power/serial clock speed management. Conversion rate is determined by the serial clock; increasing the serial clock speed reduces conversion time. Multiple shutdown modes are provided for maximum power efficiency at lower throughput rates, with maximum power consumption of 0.5 μA in full shutdown
• No pipeline delay. Uses a standard successive approximation ADC; precise control of sampling time is achieved via the CS input and single-conversion control