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Infineon CY9AF141NABGL-GK9E1

Produttore
Cod. Prod.
CY9AF141NABGL-GK9E1
Cod. LCSC
C6520202
Imballo
PFBGA-112(10x10)
Numero Cliente
Attr. chiave
ARM Cortex-M3 32 Bit 40MHz 83 PFBGA-112(10x10) Microcontrollers RoHS
Scheda Tecnicapdf iconInfineon CY9AF141NABGL-GK9E1
Parti alternative20
Esaurito
Avvisami
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
QtàPr. unit.(Solo per riferimento)Importo totale
1+$ 14.4368$ 14.44
200+$ 5.7605$ 1152.10
500+$ 5.568$ 2784.00
1,000+$ 5.4741$ 5474.10
Package Standard1980/Full Tray
Prezzo migliore per quantità maggiore?
$

Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Embedded/Microcontrollers
ProduttoreInfineon
ImballoPFBGA-112(10x10)
ADC (Bit)12bit
Operating Temperature-40℃~+85℃
Program Memory TypeFLASH
Voltage - Supply1.65V~3.6V
EEPROM-
Program Storage Size96KB
CPU CoreARM Cortex-M3
Core Size32 Bit
CPU Maximum Speed40MHz
Oscillator TypeBuilt-in+External
Number of I/O83

Descrizione

Traduzione AI

CY9A140NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, and Communication Interfaces (UART, CSIO, I²C).

Caratteristiche

Traduzione AI
  • 32-bit ARM Cortex-M3 Core
    • Processor version: r2p1
    • Up to 40 MHz Frequency Operation
    • 24-bit System timer (Sys Tick): System timer for OS task management
  • On-chip Memories
    • [Flash memory]
      • Dual operation Flash memory
        • Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously.
        • Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)
        • Work area: 32 Kbytes (lower bank)
      • Read cycle: 0 wait - cycle
      • Security function for code protection
    • [SRAM]
      • This Series on - chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I - code bus and D - code bus of Cortex - M3 core. SRAM1 is connected to System bus.
      • SRAM0: Up to 16 KB
      • SRAM1: Up to 16 KB
  • External Bus Interface
    • Supports SRAM, NOR Flash memory device
    • Up to 8 chip selects
    • 8 - /16 - bit Data width
    • Up to 25 - bit Address bit
    • Maximum area size: Up to 256 MB
    • Supports Address/Data multiplex
    • Supports external RDY function
  • Multi - function Serial Interface (Max 8 channels)
    • 4 channels with 16 steps ×9 - bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3)
    • Operation mode is selectable from the followings for each channel:
      • UART
      • CSIO
      • I2C
    • [UART]
      • Full - duplex double buffer
      • Selection with or without parity supported
      • Built - in dedicated baud rate generator
    • [CSIO]
      • Full - duplex double buffer
      • Built - in dedicated baud rate generator
      • Overrun error detection function available
    • [I2C]
      • Standard - mode (Max 100 kbps) / Fast - mode (Max 400 kbps) supported
  • DMA Controller (8 channels)
    • The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.
    • 8 independently configured and operated channels
    • Transfer can be started by software or request from the built - in peripherals
  • A/D Converter (Max 24 channels)
    • Successive Approximation type
    • Built - in 2 units
    • Conversion time: 2.0 μs @ 2.7 V to 3.6 V
    • Built - in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps)
  • Base Timer (Max 8 channels)
    • Operation mode is selectable from the followings for each channel:
      • 16 - bit PWM timer
      • 16 - bit PPG timer
      • 16 - /32 - bit reload timer
      • 16 - /32 - bit PWC timer
  • General - Purpose I/O Port
    • This series can use its pins as general - purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.
    • Capable of pull - up control per pin
    • Capable of reading pin level directly
    • Built - in the port relocate function
    • Up to 83 fast general - purpose I/O Ports@100 pin Package
  • Dual Timer (32 - /16 - bit Down Counter)
    • The Dual Timer consists of two programmable 32 - /16 - bit down counters.
    • Operation mode is selectable from the followings for each channel:
      • Free - running
      • Periodic (= Reload)
      • One - shot
  • HDMI - CEC/Remote Control Receiver (Up to 2 channels)
    • HDMI - CEC transmitter
      • Header block automatic transmission by judging Signal free
      • Generating status interrupt by detecting Arbitration lost
      • Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data
      • Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)
    • HDMI - CEC receiver
      • Automatic ACK reply function available
      • Line error detection function available
    • Remote control receiver
      • 4 bytes reception buffer
      • Repeat code detection function available
  • Real - time clock (RTC)
    • Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99.
    • The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.
    • Timer interrupt function after set time or each set time.
    • Capable of rewriting the time with continuing the time count.
    • Leap year automatic count is available.
  • Watch Counter
    • The Watch counter is used for wake up from sleep and timer mode.
    • Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
  • External Interrupt Controller Unit
    • Up to 16 external interrupt input pins
    • Include one non - maskable interrupt (NMI) input pin
  • Watchdog Timer (2 channels)
    • A watchdog timer can generate interrupts or a reset when a time - out value is reached.
    • This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog.
    • The Hardware watchdog timer is clocked by the built - in low - speed CR oscillator. Therefore, the Hardware watchdog is active in any low - power consumption modes except RTC

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