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MICROCHIP dsPIC33CK32MP102-E/M6 product image
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MICROCHIP dsPIC33CK32MP102-E/M6RoHS

Manufacturer
MICROCHIP
MPN
dsPIC33CK32MP102-E/M6
LCSC Part #
C637656
Packaging
UQFN-28-EP(4x4)
Customer #
Key Attributes
32KB 21 UQFN-28-EP(4x4) Microcontrollers RoHS
Datasheetpdf iconMICROCHIP dsPIC33CK32MP102-E/M6
In-Stock: 5
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QtyUnit PriceTotal Amount
1+$ 3.062$ 3.06
10+$ 2.9887$ 29.89
30+$ 2.9392$ 88.18
100+$ 2.8914$ 289.14
Standard Packaging91/Full Tube
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microcontrollers
ManufacturerMICROCHIP
PackagingUQFN-28-EP(4x4)
Operating Temperature-40℃~+125℃
Voltage - Supply3V~3.6V
FLASH Size32KB
Number of I/O21
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Features

AI Translation
  • 16-Bit Wide Data Path
  • Code Efficient (C and Assembly) Architecture
  • 40-Bit Wide Accumulators
  • Single-Cycle (MAC/MPY) with Dual Data Fetch
  • Single-Cycle, Mixed-Sign Multiply: 32-bit multiply support
  • Fast 6-Cycle Divide
  • Zero Overhead Looping
  • Four PWM Pairs
  • Up to 250 ps PWM Resolution
  • Dead Time for Rising and Falling Edges
  • Dead-Time Compensation
  • Clock Chopping for High-Frequency Operation
  • Fault and Current Limit Inputs
  • Flexible Trigger Configuration for ADC Triggering
  • 12-Bit Resolution
  • Two Dedicated SAR ADC Cores and One Shared SAR ADC Core
  • Up to 3.5 Msps Conversion Rate per Core
  • Dedicated Result Buffer for Each Analog Channel
  • Flexible and Independent ADC Trigger Sources
  • Four Digital Comparators
  • Four Oversampling Filters
  • Small Pin Count Packages Ranging from 28 to 48 Pins, Including UQFN as Small as 4x4 mm
  • High-Current I/O Sink/Source
  • Edge or Level Change Notification Interrupt on I/O Pins
  • Peripheral Pin Select (PPS) Remappable Pins
  • Up to 64 Kbytes Flash Memory: 10,000 erase/write cycle endurance; 20 years minimum data retention; Self-programmable under software control; Programmable code protection; Error Code Correction (ECC); Flash OTP by ICSP Write Inhibit
  • Eight Kbytes SRAM Memory: SRAM Memory Built-In Self-Test (MBIST)
  • Multiple Interrupt Vectors with Individually Programmable Priority
  • Four Sets of Interrupt Context Saving Registers which Include Accumulator and STATUS for Fast Interrupt Handling
  • Four External Interrupt Pins
  • Watchdog Timer (WDT)
  • Windowed Deadman Timer (DMT)
  • Fail-Safe Clock Monitor (FSCM) with Dedicated Oscillator for Backup
  • Selectable Oscillator Options Including: Low-Power 32 kHz RC (LPRC) Oscillator; High-precision, 8 MHz internal Fast RC (FRC) Oscillator; Primary high-speed, crystal/resonator oscillator or external clock; Primary PLL, which can be clocked from FRC or crystal oscillator; Secondary/Auxiliary PLL (APLL) for PWM and ADC
  • Low-Power Management modes (Sleep and Idle)
  • Power-on Reset and Brown-out Reset
  • On-Board Capacitorless Regulator
  • 256 Bytes of One-Time-Programmable (OTP) Memory
  • Three 4-Wire SPI modules (up to 50 Mbps): 16-byte FIFO; Variable width; I2S mode
  • Two I²C Master and Slave w/Address Masking and IPMI Support
  • Three Protocol UARTs with Automated Handling Support for: LIN 2.2; DMX; Smart card (ISO 7816); IrDA
  • Two SENT modules
  • One Dedicated 16-Bit Timer/Counter
  • Four Single Output Capture/Compare/PWM/Timer (SCCP) modules: Flexible configuration as PWM, input capture, output compare or timers; Two 16-bit timers or one 32-bit timer in each module; PWM resolution down to 4 ns; Single PWM output
  • One Multiple Output Capture/Compare/PWM/Timer (MCCP) module: Flexible configuration as PWM, input capture, output compare or timers; Two 16-bit timers or one 32-bit timer in each module; PWM resolution down to 4 ns; Up to six PWM outputs; Programmable dead time; Auto-shutdown
  • Two Quadrature Encoder Interfaces (QEI): Four inputs: Phase A, Phase B, Home, Index
  • Reference Clock Output (REFCLKO)
  • Four Configurable Logic Cells (CLC) with Internal Connections to Select Peripherals and PPS
  • 4-Channel Hardware DMA
  • 32-Bit CRC Calculation module
  • Peripheral Trigger Generator (PTG): 16 possible trigger sources to other peripheral modules; CPU independent state machine-based instruction sequencer
  • Three Fast Analog Comparators with Input Multiplexing
  • Three Operational Amplifiers
  • Three 12-Bit PDM DACs with Slope Compensation
  • One Output DAC Buffer
  • Clock Monitor System with Backup Oscillator
  • DMT (Deadman Timer)
  • ECC (Error Correcting Code)
  • WDT (Watchdog Timer)
  • CodeGuard Security
  • CRC (Cyclic Redundancy Check)
  • Flash OTP by ICSP Write Inhibit
  • RAM Memory Built-In Self-Test (MBIST)
  • Two-Speed Start-up
  • Fail-Safe Clock Monitoring (FSCM)
  • Backup FRC (BFRC)
  • Capless Internal Voltage Regulator
  • Virtual Pins for Redundancy and Monitoring
  • Class B Safety Library – IEC 60730
  • For ASIL B and Beyond Applications – ISO 26262
  • FMEDA Computation Spreadsheet (Evaluation of Random Hardware Failures Metric)
  • Functional Safety Manual
  • Functional Safety Diagnostics Suite
  • AEC-Q100 REV-H (Grade 1: -40℃ to +125℃) Compliant
  • AEC-Q100 REV-H (Grade 0: -40℃ to +150℃) Compliant
  • Three Programming and Debugging Interfaces: Two-wire ICSP interface with non-intrusive access and real-time data exchange with application
  • Three Complex, Five Simple Breakpoints
  • IEEE Standard 1149.2 Compatible (JTAG) Boundary Scan