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ST STM32H725VGH3 product image
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ST STM32H725VGH3RoHS

Manufacturer
ST
MPN
STM32H725VGH3
LCSC Part #
C6303469
Packaging
TFBGA-100(8x8)
Customer #
Key Attributes
ARM Cortex-M7 32 Bit 550MHz 74 TFBGA-100(8x8) Microcontrollers RoHS
Datasheetpdf iconST STM32H725VGH3
In-Stock: 1
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QtyUnit PriceTotal Amount
1+$ 19.9048$ 19.90
10+$ 18.9917$ 189.92
30+$ 17.4089$ 522.27
100+$ 16.0282$ 1602.82
Standard Packaging348/Full Tray
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microcontrollers
ManufacturerST
PackagingTFBGA-100(8x8)
DAC (Bit)12bit
ADC (Bit)16bit
Operating Temperature-40℃~+125℃
Program Memory TypeFLASH
Voltage - Supply1.62V~3.6V
EEPROM-
Program Storage Size1MB
CPU CoreARM Cortex-M7
Core Size32 Bit
CPU Maximum Speed550MHz
Oscillator TypeBuilt-in+External
Number of I/O74
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Features

AI Translation
  • Includes ST state-of-the-art patented technology
  • 32-bit Arm Cortex-M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte instruction cache allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 550 MHz, MPU, 1177 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
  • Up to 1 Mbyte of embedded Flash memory with ECC SRAM: total 564 Kbytes all with ECC, including 128 Kbytes of data TCM RAM for critical realtime data + 432 Kbytes of system RAM (up to 256 Kbytes can remap on instruction TCM RAM for critical real time instructions) + 4 Kbytes of backup SRAM (available in the lowest-power modes)
  • Flexible external memory controller with up to 24-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
  • 2 x Octo-SPI interface with XiP
  • 2 x SD/SDIO/MMC interface
  • Bootloader
  • Chrom-ART Accelerator graphical hardware accelerator enabling enhanced graphical user interface to reduce CPU load
  • LCD-TFT controller supporting up to XGA resolution
  • 1.62 V to 3.6 V application supply and I/O
  • POR, PDR, PVD and BOR
  • Dedicated USB power
  • Embedded DCDC and LDO regulator (*)VFQFPN68 variant is DCDC only
  • Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
  • External oscillators: 4 - 50 MHz HSE, 32.768 kHz LSE
  • Sleep, Stop and Standby modes
  • V_BAT supply for RTC, 32 x 32-bit backup registers
  • 2 x 16-bit ADC, up to 3.6 MSPS in 16-bit: up to 22 channels and 7.2 MSPS in doubleinterleaved mode
  • 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12 channels
  • 2 x comparators
  • 2 x operational amplifier GBW = 8 MHz
  • 2 x 12-bit D/A converters
  • 8 channels/4 filters for Digital filters for sigma delta modulator (DFSDM)
  • 4 DMA controllers to offload the CPU
  • 1 x MDMA with linked list support
  • 2 x dual-port DMAs with FIFO
  • 1 x basic DMA with request router capabilities
  • 24 timers: Seventeen 16-bit (including 5 x low power 16-bit timer available in stop mode) and four 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
  • 2 x watchdogs, 1 x SysTick timer
  • SWD and JTAG interfaces
  • 2-Kbyte embedded trace buffer
  • Up to 128 I/O ports with interrupt capability
  • Up to 35 communication interfaces: Up to 5 x I2C FM+ interfaces (SMBus/PMBus), Up to 5 USARTs/5 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1x LPUART, Up to 6 SPIs with 4 with muxed duplex I2S for audio class accuracy via internal audio PLL or external clock and up to 5 x SP (from 5 x USART when configured in synchronous mode), 2 x SAI (serial audio interface), 1 x FD/TT-CAN and 2 x FD-CAN, 8- to 14-bit camera interface, 16-bit parallel slave synchronous interface, SPDIF-IN interface, HDMI-CEC, Ethernet MAC interface with DMA controller, USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip FS PHY and ULPI for external HS PHY, SWPMI single-wire protocol master I/F, MDIO slave interface
  • CORDIC for trigonometric functions acceleration
  • FMAC: Filter mathematical accelerator
  • Digital temperature sensor
  • True random number generator
  • CRC calculation unit
  • RTC with sub-second accuracy and hardware calendar
  • ROP, PC-ROP, tamper detection
  • 96-bit unique ID
  • All packages are ECOPACK2 compliant