MICROCHIP AT91SAM9XE512B-QU

The Atmel | SMART SAM9XE microcontroller series is based on the integration of an ARM926EJ-S processor with fast ROM, RAM and Flash, and a wide range of peripherals. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits, a security bit and MMU protect the firmware from accidental overwrite and preserve its confidentiality. The SAM9XE series embeds an Ethernet MAC, one USB Device Port, and a USB Host Controller. It also integrates several standard peripherals, including six UARTs, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and a MultiMedia/SD Card Interface. The SAM9XE system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator. The SAM9XE series architecture includes a 6-layer matrix, allowing a maximum internal bandwidth of six 32-bit buses. It also features an External Bus Interface capable of interfacing with a wide range of memory devices. The pinout and ball-out are fully compatible with the Atmel | SMART SAM9260 eMPU with the exception that the pin BMS is replaced by the pin ERASE.

• Incorporates the ARM926EJ-S ARM Thumb Processor
• DSP instruction Extensions, ARM Jazelle Technology for Java Acceleration
• 8 KB Data Cache, 16 KB Instruction Cache, Write Buffer
• 200 MIPS at 180 MHz
• Memory Management Unit
• EmbeddedICE, Debug Communication Channel Support
• One 32 KB Internal ROM, Single-cycle Access at Maximum Matrix Speed
• One 32 KB (SAM9XE256 and SAM9XE512) or 16 KB (SAM9XE128) Internal SRAM, Single-cycle Access at Maximum Matrix Speed
• Internal High-speed Flash: 128 KB (SAM9XE128), 256 KB (SAM9XE256) or 512 KB (SAM9XE512) organized in 256, 512 or 1024 pages of 512 bytes respectively
• 128-bit Wide Access Fast Read Time: 45 ns
• Page Programming Time: 4 ms, Including Page Auto-erase
• Full Erase Time: 10 ms
• 10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash Security Bit
• Enhanced Embedded Flash Controller (EEFC) Interface of the Flash Block with the 32-bit Internal Bus Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory Interface
• External Bus Interface (EBI) Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash
• USB 2.0 Full Speed (12 Mbit/s) Device Port On-chip Transceiver, 2688-byte Configurable Integrated DPRAM
• USB 2.0 Full Speed (12 Mbit/s) Host Single Port in 208-pin PQFP Device and Double Port in 217-ball LFBGA Device
• Single or Dual On-chip Transceivers Integrated FIFOs and Dedicated DMA Channels
• Ethernet MAC 10/100 Base-T Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)
• 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
• Image Sensor Interface (ISI) ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
• 12-bit Data Interface for Support of High Sensibility Sensors
• SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
• Bus Matrix Six 32-bit-layer Matrix Remap Command
• Fully-featured System Controller, including
• Reset Controller (RSTC), Shutdown Controller (SHDWC)
• 128-bit (4×32-bit) General Purpose Backup Registers
• Clock Generator and Power Management Controller
• Advanced Interrupt Controller (AIC) and Debug Unit (DBGU)
• Periodic Interval Timer (PIT), Watchdog Timer (WDT) and Real-time Timer (RTT)
• Reset Controller (RSTC) Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control
• Clock Generator (CKGR) Selectable 32768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock
• 3 to 20 MHz On-chip Oscillator, One Up to 240 MHz PLL and One Up to 100 MHz PLL
• Power Management Controller (PMC) Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
• Two Programmable External Clock Signals
• Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
• Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
• Debug Unit (DBGU) 2-wire UART and support for Debug Communication Channel, Programmable ICE Access Prevention Mode for General Purpose Two-wire UART Serial Communication
• Periodic Interval Timer (PIT) 20-bit Interval Timer Plus 12-bit Interval Counter
• Watchdog Timer (WDT) Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
• Real-time Timer (RTT) 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
• One 4-channel 10-bit Analog-to-Digital Converter
• Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC) 96 Programmable I/O Lines
• Multiplexed with up to Two Peripheral I/Os
• Input Change Interrupt Capability on Each I/O Line
• Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
• Peripheral DMA Controller (PDC) Channels
• Two-slot Multimedia Card Interface (MCI) SDCard/SDIO and MultiMediaCard Compliant
• Automatic Protocol Control and Fast Automatic Data Transfers with PDC
• One Synchronous Serial Controllers (SSC) Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
• I²S Analog Interface Support, Time Division Multiplex Support
• High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Four Universal Synchronous/Asynchronous Receiver Transmitters (USART) Individual Baud Rate Generator
• IrDA Infrared Modulation/Demodulation, Manchester Encoding/Decoding
• Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
• Full Modem Signal Control on USART0
• One 2-wire UART
• Two Master/Slave Serial Peripheral