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EDA ModelsEasyEDA
MICROCHIP dsPIC33CH512MP206-I/MR
| Manufacturer | |
| MPN | dsPIC33CH512MP206-I/MR |
| LCSC Part # | C614568 |
| Packaging | QFN-64-EP(9x9) |
| Customer # | |
| Key Attributes | 584KB 53 QFN-64-EP(9x9) Microcontrollers RoHS |
| Datasheet |  MICROCHIP dsPIC33CH512MP206-I/MR |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | QFN-64-EP(9x9) | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 3V~3.6V | |
| FLASH Size | 584KB | |
| Number of I/O | 53 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | QFN-64-EP(9x9) | |
| Operating Temperature | -40℃~+85℃ |
| Type | Description | |
|---|---|---|
| Voltage - Supply | 3V~3.6V | |
| FLASH Size | 584KB | |
| Number of I/O | 53 |
Report an ErrorShow similar products (0) >
Features
AI Translation
- Master/Slave Core Operation
- Independent Peripherals for Master Core and Slave Core
- Configurable Shared Resources for Master Core and Slave Core
- Master Core with 256 - 512 Kbytes of Program Flash with ECC and 32 - 48K Data RAM with BIST
- Slave Core with 72 Kbytes of Program RAM (PRAM) with ECC and 16K Data RAM with BIST
- Fast 6 - Cycle Divide
- LiveUpdate
- Message Boxes and FIFO to Communicate Between Master and Slave (MSI)
- Code Efficient (C and Assembly) Architecture
- 40 - Bit Wide Accumulators
- Single - Cycle (MAC/MPY) with Dual Data Fetch
- Single - Cycle, Mixed - Sign MUL Plus Hardware Divide
- 32 - Bit Multiply Support
- Five Sets of Interrupt Context Selected Registers per Core for Fast Interrupt Response
- Zero Overhead Looping
- Internal Oscillator
- Programmable PLLs and Oscillator Clock Sources
- Master Reference Clock Output
- Slave Reference Clock Output
- Fail - Safe Clock Monitor (FSCM)
- Fast Wake - up and Start - up
- Backup Internal Oscillator
- LPRC Oscillator
- Low - Power Management Modes (Sleep, Idle, Doze)
- Integrated Power - on Reset and Brown - out Res
- Up to Twelve PWM Channels: Four channels for Master, Eight channels for Slave
- 250 ps PWM Resolution
- Two General Purpose 16 - Bit Timers: One each for Master and Slave
- Peripheral Trigger Generator (PTG) Module: One module for Master, Slave can interrupt on select PTG sources, Useful for automating complex sequences
- Twelve SCCP Modules: Eight modules for Master, Four modules for Slave, Timer, Capture/Compare and PWM modes, 16 or 32 - bit time base, 16 or 32 - bit capture, 4 - deep capture buffer, Fully asynchronous operation, available in Sleep modes
- Four ADC Modules: One module for Master core, Three modules for Slave core, 12 - bit, 3.25 Msps ADC, Up to 18 conversion channels, 250 ns conversion latency
- Four DAC/Analog Comparator Modules: One module for Master core, Three modules for Slave core, 12 - bit DACs with hardware slope compensation, 15 ns analog comparators
- Three PGA Modules: Three modules for Slave core, Can be read by Master ADC
- Shared DAC/Analog Output: DAC/analog comparator outputs, PGA outputs
- Three UART Modules: Two modules for Master core, One module for Slave core, Support for DMX, LIN/J2602 protocols
- Three 4 - Wire SPI/I²S Modules: Two modules for Master core, One module for Slave core
- Two CAN Flexible Data - Rate (FD) Modules for the Master Core
- Three I²C Modules: Two modules for Master, One module for Slave, Support for SMBus
- PPS to Allow Function Remap
- Programmable Cyclic Redundancy Check (CRC) for the Master
- Two SENT Modules for the Master
- Eight DMA Channels: Six DMA channels available for the Master core, Two DMA channels available for the Slave core
- In - Circuit and In - Application Programming
- Simultaneous Debugging Support for Master and Slave Cores
- Master Only Debug and Slave Only Debug Support
- Master with Three Complex, Five Simple Breakpoints and Slave with One Complex, Two Simple Breakpoints
- IEEE 1149.2 Compatible (JTAG) Boundary Scan
- Trace Buffer and Run - Time Watch
- DMT (Deadman Timer)
- ECC (Error Correcting Code)
- WDT (Watchdog Timer)
- CodeGuard Security
- CRC (Cyclic Redundancy Check)
- ICSP Write Inhibit
- RAM Memory Built - In Self Test (MBIST)
- Two - Speed Start - up
- Fail - Safe Clock Monitoring (FSCM)
- Backup FRC (BFRC)
- Capless Internal Voltage Regulator
- Virtual Pins for Redundancy and Monitoring
- AEC - Q100 REVG (Grade 1: - 40℃ to + 125℃) Compliant
- Class B Safety Library, IEC 60730
Applications
AI Translation
- DC/DC Converters
- AC/DC power supplies
- Uninterruptable Power Supply (UPS)
- Motor Control: BLDC, PMSM, SR, ACIM
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 7.0259 | $ 7.03 |
| 200+ | $ 2.7196 | $ 543.92 |
| 500+ | $ 2.6239 | $ 1311.95 |
| 1,000+ | $ 2.5761 | $ 2576.10 |
Standard Packaging40/Full Tube | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | QFN-64-EP(9x9) | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 3V~3.6V | |
| FLASH Size | 584KB | |
| Number of I/O | 53 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | QFN-64-EP(9x9) | |
| Operating Temperature | -40℃~+85℃ |
| Type | Description | |
|---|---|---|
| Voltage - Supply | 3V~3.6V | |
| FLASH Size | 584KB | |
| Number of I/O | 53 |
Report an ErrorShow similar products (0) >
Features
AI Translation
- Master/Slave Core Operation
- Independent Peripherals for Master Core and Slave Core
- Configurable Shared Resources for Master Core and Slave Core
- Master Core with 256 - 512 Kbytes of Program Flash with ECC and 32 - 48K Data RAM with BIST
- Slave Core with 72 Kbytes of Program RAM (PRAM) with ECC and 16K Data RAM with BIST
- Fast 6 - Cycle Divide
- LiveUpdate
- Message Boxes and FIFO to Communicate Between Master and Slave (MSI)
- Code Efficient (C and Assembly) Architecture
- 40 - Bit Wide Accumulators
- Single - Cycle (MAC/MPY) with Dual Data Fetch
- Single - Cycle, Mixed - Sign MUL Plus Hardware Divide
- 32 - Bit Multiply Support
- Five Sets of Interrupt Context Selected Registers per Core for Fast Interrupt Response
- Zero Overhead Looping
- Internal Oscillator
- Programmable PLLs and Oscillator Clock Sources
- Master Reference Clock Output
- Slave Reference Clock Output
- Fail - Safe Clock Monitor (FSCM)
- Fast Wake - up and Start - up
- Backup Internal Oscillator
- LPRC Oscillator
- Low - Power Management Modes (Sleep, Idle, Doze)
- Integrated Power - on Reset and Brown - out Res
- Up to Twelve PWM Channels: Four channels for Master, Eight channels for Slave
- 250 ps PWM Resolution
- Two General Purpose 16 - Bit Timers: One each for Master and Slave
- Peripheral Trigger Generator (PTG) Module: One module for Master, Slave can interrupt on select PTG sources, Useful for automating complex sequences
- Twelve SCCP Modules: Eight modules for Master, Four modules for Slave, Timer, Capture/Compare and PWM modes, 16 or 32 - bit time base, 16 or 32 - bit capture, 4 - deep capture buffer, Fully asynchronous operation, available in Sleep modes
- Four ADC Modules: One module for Master core, Three modules for Slave core, 12 - bit, 3.25 Msps ADC, Up to 18 conversion channels, 250 ns conversion latency
- Four DAC/Analog Comparator Modules: One module for Master core, Three modules for Slave core, 12 - bit DACs with hardware slope compensation, 15 ns analog comparators
- Three PGA Modules: Three modules for Slave core, Can be read by Master ADC
- Shared DAC/Analog Output: DAC/analog comparator outputs, PGA outputs
- Three UART Modules: Two modules for Master core, One module for Slave core, Support for DMX, LIN/J2602 protocols
- Three 4 - Wire SPI/I²S Modules: Two modules for Master core, One module for Slave core
- Two CAN Flexible Data - Rate (FD) Modules for the Master Core
- Three I²C Modules: Two modules for Master, One module for Slave, Support for SMBus
- PPS to Allow Function Remap
- Programmable Cyclic Redundancy Check (CRC) for the Master
- Two SENT Modules for the Master
- Eight DMA Channels: Six DMA channels available for the Master core, Two DMA channels available for the Slave core
- In - Circuit and In - Application Programming
- Simultaneous Debugging Support for Master and Slave Cores
- Master Only Debug and Slave Only Debug Support
- Master with Three Complex, Five Simple Breakpoints and Slave with One Complex, Two Simple Breakpoints
- IEEE 1149.2 Compatible (JTAG) Boundary Scan
- Trace Buffer and Run - Time Watch
- DMT (Deadman Timer)
- ECC (Error Correcting Code)
- WDT (Watchdog Timer)
- CodeGuard Security
- CRC (Cyclic Redundancy Check)
- ICSP Write Inhibit
- RAM Memory Built - In Self Test (MBIST)
- Two - Speed Start - up
- Fail - Safe Clock Monitoring (FSCM)
- Backup FRC (BFRC)
- Capless Internal Voltage Regulator
- Virtual Pins for Redundancy and Monitoring
- AEC - Q100 REVG (Grade 1: - 40℃ to + 125℃) Compliant
- Class B Safety Library, IEC 60730
Applications
AI Translation
- DC/DC Converters
- AC/DC power supplies
- Uninterruptable Power Supply (UPS)
- Motor Control: BLDC, PMSM, SR, ACIM
C614568 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |