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XINLUDA XD74LS192RoHS

Manufacturer
XINLUDAAsian Brands
MPN
XD74LS192
LCSC Part #
C609768
Packaging
DIP-16
Customer #
Key Attributes
SYNCHRONOUS 4-BIT COUNTERS (DUAL CLOCK WITH CLEAR)
Datasheetpdf iconXINLUDA XD74LS192
In-Stock: 5
5 In stock, ships now
Minimum: 5Multiple: 5Sales Unit: Piece
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QtyUnit PriceTotal Amount
5+$ 0.4065$ 2.03
50+$ 0.3138$ 15.69
150+$ 0.2795$ 41.93
500+$ 0.2368$ 118.40
2,000+$ 0.2177$ 435.40
5,000+$ 0.2063$ 1031.50
Standard Packaging25/Full Tube
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Counters, Dividers
ManufacturerXINLUDA
PackagingDIP-16
Logic Family74LS
Voltage - Supply4.75V~5.25V
DirectionUp Counter;Down Counter
Trigger TypeRising Edge
TimingSynchronous
ResetAsynchronous
Operating Temperature0℃~+70℃
Number of Elements1
Propagation Delay38ns
Count Rate25MHz
FeaturesProgrammable divide ratio;Multi-mode counting;Synchronous counting;Asynchronous parallel load;Reset function;Cascade counter

Introduction

AI Translation

These monolithic circuits are synchronous reversible (up/down) counters having a complexity of 55 equivalent gates. The ’LS193 is 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple-clock) counters. The outputs of the four master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is high. All four counters are fully programmable; that is, each output may be preset to either level by entering the desired data at the data inputs while the load input is low. The output will change to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements. This reduces the number of clock drivers, etc., required for long words. These counters were designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up and down-counting functions. The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count-down input when an overflow condition exists. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs respectively of the succeeding counter.

Features

AI Translation
  • Cascading Circuitry Provided Internally
  • Synchronous Operation
  • Individual Preset to Each Flip-Flop
  • Fully Independent Clear Input