Nexperia 74HC40105PW,112

The 74HC40105 and 74HCT40105 are first-in first-out (FIFO) "elastic" storage registers capable of storing 16 four-bit words. They can handle input and output data at different shift rates, making them particularly suitable as buffers between asynchronous systems. Each word position in the register is clocked by a control flip-flop that stores a tag bit. A logic 1 indicates that the position is filled with data, while a logic 0 indicates that the position is empty. Each control flip-flop monitors the state of the preceding flip-flop and communicates its own state to the following flip-flop. When a control flip-flop is in the logic 0 state and detects a logic 1 in the preceding flip-flop, it generates a clock pulse. This clock pulse transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to logic 0. The first and last control flip-flops have buffered outputs. All empty positions automatically "bubble" toward the input, while all valid data ripples toward the output. Consequently, the state of the first control flip-flop (Data Input Ready output — DIR) indicates whether the FIFO is full. The state of the last flip-flop (Data Output Ready output — DOR) indicates whether the FIFO contains data. When the earliest data is removed from the bottom of the data stack (output end), all subsequently entered data automatically ripples toward the output. The inputs incorporate clamp diodes, allowing the inputs to be connected to voltages exceeding VCC through current-limiting resistors.

• Independent asynchronous inputs and outputs
• Expandable in either direction
• Reset capability
• Status indication on inputs and outputs
• Three-state outputs
• Input levels: CMOS for 74HC40105; TTL for 74HCT40105
• Three-state outputs
• Compliant with JEDEC standard JESD7A
• ESD protection: HBM JESD22-A114F exceeds 2000 V; MM JESD22-A115-A exceeds 200 V
• Multiple package options
• Operating temperature range: -40°C to +85°C and -40°C to +125°C