GSI Technology GS864018GT-250I

GS864018/32/36T is a 75,497,472-bit high-performance synchronous SRAM with a 2-bit burst address counter. Although this type was originally developed for Level 2 cache applications supporting high-performance CPUs, the device can now be used in synchronous SRAM applications ranging from DSP main memory to network chipset support. Address, data I/O, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous, controlled by a positive edge-triggered clock input (CK). Output enable (G) and power-down control (ZZ) are asynchronous inputs. A burst cycle can be initiated by the ADSP (active low) or ADSC (active low) input. In burst mode, subsequent burst addresses are generated internally and controlled by ADV (active low). The burst address counter can be configured to count in either linear or interleaved order via the Linear Burst Order (LBO) input. The burst function is not mandatory; a new address can be loaded every cycle without degrading device performance. The function of the data output register can be controlled by the user via the FT mode pin (pin 14). Pulling the FT mode pin low places the RAM in flow-through mode, allowing output data to bypass the data output register; pulling FT high places the RAM in pipeline mode, activating the rising edge-triggered data output register. Byte write operations are performed by combining the byte write enable (BW) input with one or more individual byte write signals (Bx). In addition, the global write (GW) can be used to write all bytes at once, regardless of the byte write control inputs. Low-power (sleep mode) can be achieved by asserting the ZZ signal high or stopping the clock (CK); memory data is retained during sleep mode. The GS864018/32/36T operates from a 2.5V or 3.3V supply, with all inputs compatible with both 3.3V and 2.5V. A separate output supply (VDDQ) pin is provided to decouple output noise from internal circuitry and is compatible with both 3.3V and 2.5V.

• FT pin for user-configurable flow-through or pipelined operation
• Single-cycle deselect (SCD) operation
• 2.5V or 3.3V +10%/-10% core supply
• 2.5V or 3.3V I/O supply
• LBO pin for linear or interleaved burst mode
• Internal input resistors on mode pins allow pins to float
• Default configuration: interleaved pipeline mode
• Byte write (BW) and/or global write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC standard 100-pin TQFP package
• RoHS-compliant 100-pin TQFP package available

• GS864018/32/36T is a 75,497,472-bit high-performance synchronous SRAM with a 2-bit burst address counter.
• Although originally developed to support L2 cache applications for high-performance CPUs, it is now deployed across synchronous SRAM applications ranging from DSP main memory to network chipset support.