GSI Technology GS8662T18BGD-400I
| Manufacturer | GSI TechnologyAsian Brands |
| MPN | GS8662T18BGD-400I |
| LCSC Part # | C5720127 |
| Packaging | FPBGA-165(13x15) |
| Customer # | |
| Key Attributes | 1.7V~1.9V FPBGA-165(13x15) Memory RoHS |
| Datasheet |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | GSI Technology | |
| Packaging | FPBGA-165(13x15) | |
| Operating Temperature | -40℃~+100℃ | |
| Features | Built-in delay-locked loop;Boundary scan (JTAG) function | |
| Memory Size | - | |
| Voltage - Supply | 1.7V~1.9V | |
| Access Time | - | |
| Current - Supply | 635mA | |
| Standby Supply Current | 255mA | |
| Interface | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | GSI Technology | |
| Packaging | FPBGA-165(13x15) | |
| Operating Temperature | -40℃~+100℃ | |
| Features | Built-in delay-locked loop;Boundary scan (JTAG) function | |
| Memory Size | - |
| Type | Description | |
|---|---|---|
| Voltage - Supply | 1.7V~1.9V | |
| Access Time | - | |
| Current - Supply | 635mA | |
| Standby Supply Current | 255mA | |
| Interface | - |
Report an ErrorShow similar products (0) >
Introduction
AI Translation
GS8662T08/09/18/36BD complies with the SigmaDDR-II SRAM pinout standard for general-purpose I/O synchronous SRAM, featuring 75,497,472 bits (72Mb) of SRAM. They are part of a low-power, low-voltage HSTL I/O SRAM family, designed to operate at the speeds required for cost-effective, high-performance networking systems.
Features
AI Translation
- Synchronous read/write SigmaDDR interface
- General-purpose I/O bus
- JEDEC standard pinout and package
- Double data rate interface
- Byte-write (x36, x18, and x9) and nibble-write (x8) capability
- Burst length of 2 read/write operations
- Core supply voltage: 1.8V +100/-100 mV
- HSTL interface: 1.5V or 1.8V
- Pipelined read with self-timed delayed write
- Fully coherent read/write pipeline
- ZQ pin for programmable output drive strength
- IEEE 1149.1 JTAG-compliant boundary scan
- Pin-compatible with existing 9Mb, 18Mb, 36Mb, and 72Mb devices
- 165-ball, 13mm × 15mm, 1mm ball pitch BGA package
- Available in RoHS-compliant 165-ball BGA package
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 424.6277 | $ 424.63 |
| 195+ | $ 169.4302 | $ 33038.89 |
| 495+ | $ 163.7684 | $ 81065.36 |
| 1,005+ | $ 160.9701 | $ 161774.95 |
Standard Packaging15/Full Tray | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | GSI Technology | |
| Packaging | FPBGA-165(13x15) | |
| Operating Temperature | -40℃~+100℃ | |
| Features | Built-in delay-locked loop;Boundary scan (JTAG) function | |
| Memory Size | - | |
| Voltage - Supply | 1.7V~1.9V | |
| Access Time | - | |
| Current - Supply | 635mA | |
| Standby Supply Current | 255mA | |
| Interface | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | GSI Technology | |
| Packaging | FPBGA-165(13x15) | |
| Operating Temperature | -40℃~+100℃ | |
| Features | Built-in delay-locked loop;Boundary scan (JTAG) function | |
| Memory Size | - |
| Type | Description | |
|---|---|---|
| Voltage - Supply | 1.7V~1.9V | |
| Access Time | - | |
| Current - Supply | 635mA | |
| Standby Supply Current | 255mA | |
| Interface | - |
Report an ErrorShow similar products (0) >
Introduction
AI Translation
GS8662T08/09/18/36BD complies with the SigmaDDR-II SRAM pinout standard for general-purpose I/O synchronous SRAM, featuring 75,497,472 bits (72Mb) of SRAM. They are part of a low-power, low-voltage HSTL I/O SRAM family, designed to operate at the speeds required for cost-effective, high-performance networking systems.
Features
AI Translation
- Synchronous read/write SigmaDDR interface
- General-purpose I/O bus
- JEDEC standard pinout and package
- Double data rate interface
- Byte-write (x36, x18, and x9) and nibble-write (x8) capability
- Burst length of 2 read/write operations
- Core supply voltage: 1.8V +100/-100 mV
- HSTL interface: 1.5V or 1.8V
- Pipelined read with self-timed delayed write
- Fully coherent read/write pipeline
- ZQ pin for programmable output drive strength
- IEEE 1149.1 JTAG-compliant boundary scan
- Pin-compatible with existing 9Mb, 18Mb, 36Mb, and 72Mb devices
- 165-ball, 13mm × 15mm, 1mm ball pitch BGA package
- Available in RoHS-compliant 165-ball BGA package
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991B2B |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991B2B |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |

