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Nexperia 74AUP2G86GS,115 product image
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Nexperia 74AUP2G86GS,115

Manufacturer
MPN
74AUP2G86GS,115
LCSC Part #
C546159
Packaging
XSON-8(1x1.4)
Customer #
Key Attributes
Schmitt trigger 800mV~3.6V 7.1ns@3.3V,30pF 500nA XSON-8(1x1.4) Gates and Inverters RoHS
Datasheetpdf iconNexperia 74AUP2G86GS,115
RoHS Compliance1 documents available
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QtyUnit Price(Reference Only)Total Amount
1+$ 1.0373$ 1.04
200+$ 0.4014$ 80.28
500+$ 0.3875$ 193.75
1,000+$ 0.3813$ 381.30
Standard Packaging5000/Full Reel
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters
ManufacturerNexperia
PackagingXSON-8(1x1.4)
output type-
Input TypeSchmitt trigger
Logic Family74AUP Series
Voltage - Supply800mV~3.6V
Output Logic Level - Low-
Propagation Delay7.1ns@3.3V,30pF
FeaturesLocal shutdown mode
Operating Temperature-40℃~+125℃
Input Logic Level - Low700mV~900mV
Input Logic Level - High1.6V~2V
Output Logic Level - High-
Quiescent Current(Iq)500nA
Number of Channels2;2
Current - Output High(IOH)4mA
Current - Output Low(IOL)4mA

Introduction

AI Translation

The 74AUP2G86 provides the dual 2-input EXCLUSIVE-OR function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Features

AI Translation
  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V), JESD8-11 (0.9 V to 1.65 V), JESD8-7 (1.2 V to 1.95 V), JESD8-5 (1.8 V to 2.7 V), JESD8-B (2.7 V to 3.6 V)
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10% of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
  • Low-power dual 2-input EXCLUSIVE-OR gate