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Nexperia 74AUP1G373GW-Q100H product image
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Nexperia 74AUP1G373GW-Q100HRoHS

Manufacturer
Nexperia
MPN
74AUP1G373GW-Q100H
LCSC Part #
C545852
Packaging
TSSOP-6-1.3mm
Customer #
Key Attributes
Low-power D-type transparent latch; 3-state
Datasheetpdf iconNexperia 74AUP1G373GW-Q100H
In-Stock: 2,955
2,955 In stock, ships now
Minimum: 5Multiple: 5Sales Unit: Piece
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QtyUnit PriceTotal Amount
5+$ 0.3552$ 1.78
50+$ 0.2831$ 14.16
150+$ 0.2522$ 37.83
500+$ 0.2136$ 106.80
3,000+$ 0.1964$ 589.20
6,000+$ 0.1861$ 1116.60
Standard Packaging3000/Full Reel
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Latches
ManufacturerNexperia
PackagingTSSOP-6-1.3mm
Quiescent Current0.9uA
Series74AUP
Logic TypeD Latch
Voltage - Supply0.8V~3.6V
Current - Output Low(IOL)4mA
Operating Temperature-40℃~+125℃
Output TypeTri-State
Current - Output High(IOH)4mA
Setup Time-0.1ns;0.3ns
Number of Gates1
Hold Time-0.1ns
Propagation Delay2.5ns
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Introduction

AI Translation

The 74AUP1G373-Q100 is a single D-type transparent latch; 3-state. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features

AI Translation
  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
  • Specified from -40 ℃ to +85 ℃ and from -40 ℃ to +125 ℃
  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • CMOS low power dissipation
  • Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V)
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Overvoltage tolerant inputs to 3.6 V
  • Low noise overshoot and undershoot <10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V