LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
Cart
TI CD4023BNSR product image
Images for reference only

TI CD4023BNSRRoHS

Manufacturer
TI
MPN
CD4023BNSR
LCSC Part #
C5217673
Packaging
SO(NS)-14
Customer #
Key Attributes
CMOS NAND GATES High-Voltage Types
Datasheetpdf iconTI CD4023BNSR
In-Stock: 1
1 In stock, ships now
Minimum: 1Multiple: 1Sales Unit: Piece
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 1.0124$ 1.01
10+$ 0.9896$ 9.90
30+$ 0.9733$ 29.20
100+$ 0.9587$ 95.87
Standard Packaging2000/Full Reel
Better price for more quantity?
$

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters
ManufacturerTI
PackagingSO(NS)-14
Features-
Logic FamilyCD4
Input Logic Level - High3.5V;7V;11V
Input Logic Level - Low1.5V;3V;4V
Operating Temperature-55℃~+125℃
Output Logic Level - High4.95V;9.95V;14.95V
Quiescent Current(Iq)5mA
Voltage - Supply3V~18V
Current - Output High(IOH)6.8mA
Number of Channels3;3
Output Logic Level - Low50mV
Propagation Delay45ns@15V,50pF
Current - Output Low(IOL)6.8mA
Report an ErrorShow similar products (0) >

Introduction

AI Translation

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMoS gates. All inputs and outputs are buffered. The CD4011B, CD4012B, and CD4023B types are supplied in 14 - lead hermetic dual - in - line ceramic packages (F3A suffix), 14 - lead dual - in - line plastic packages (E suffix), 14 - lead small - outline packages (M, MT, M96, and NSR suffixes), and 14 - lead thin shrink small - outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14 - lead thin shrink small - outline packages (PW suffix).

Features

AI Translation
  • Propagation delay time = ±50 ns (typ.) at cL = 50 pF, VDD = 10 V
  • Buffered inputs and outputs
  • Standardized symmetrical output characteristics
  • Maximum input current of ±1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
  • 100% tested for quiescent current at 20 V
  • 5 - V, 10 - V, and 15 - V parametric ratings
  • Noise margin (over full package temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOs Devices"