Motorcomm YT9215SC

YT9215SC is a high-performance 5+2 port Gigabit Ethernet switch controller in an LQFP128 E-PAD package. It integrates five PHY transceivers supporting 1000Base-T/100Base-T/10Base-Te, plus two additional MAC ports for specific applications, with support for MII, RMII, RGMII, SGMII, 1000Base-X, 100Base-FX, or 2500Base-X interfaces. The device also embeds a RISC-V microprocessor. The integrated Gigabit PHY transceivers comply with IEEE 802.3 specifications for 10BASE-Te, 100BASE-TX, and 1000BASE-T, and support Motorcomm proprietary LRE100-4 features, enabling auto-negotiation and link establishment with LRE100-4-compatible link partners. The LRE100-4 feature enables extended transmission distances of up to 400 meters at 100Mbps over Cat5e cables. The YT9215SC's extended GMAC1 and GMAC2 support xMII or SerDes interfaces for connecting external PHY transceivers, MACs, external CPUs, or RISC processors in specific applications, and also support direct optical port access via SerDes. xMII refers to RGMII, MII, and RMII. SerDes supports IEEE 100Base-FX, IEEE 1000Base-X, and IEEE 2500Base-X standards. The YT9215SC integrates a 4K-entry lookup table using an efficient hash algorithm for address lookup and learning, with each entry configurable as a static entry. It supports IEEE 802.1Q VLAN with a 4K-entry VLAN table, offering multiple VLAN classification methods including port-based, protocol-and-port-based, VLAN translation, and flow-based, with MAC-based and IP subnet-based VLAN also configurable. It further supports Independent VLAN Learning and Shared VLAN Learning for flexible network topology design. The YT9215SC supports standard 802.3x flow control frames in full-duplex mode and an optional backpressure mechanism in half-duplex mode. It determines when to trigger flow control by checking system resource availability, and supports storm control. For flexible traffic classification, the YT9215SC supports 384 hardware-entry ACL rule checks with multiple action options. These 384 entries are organized into 48 rows, each containing 8 entries. To support longer rules, the 8 entries in each row can be combined in any configuration to extend rules. ACL rule checking can be individually enabled or disabled per port. ACL rule keys can be based on a packet's physical port, Layer 2, Layer 3, and Layer 4 information. When an ACL rule is matched, configurable actions include drop, permit, redirect, and mirror, along with the ability to modify the priority or DSCP value in the 802.1q/Q tag, and apply rate policing.

• High-performance, non-blocking 7-port Ethernet switch with integrated features:
• Five 10/100/1000Mbps PHY transceivers with advanced virtual cable test diagnostics; each PHY supports 10/100/1000M full-duplex connections (half-duplex supported in 10/100M mode only), full/half-duplex operation, IEEE 802.3x flow control, and back-pressure.
• Interfaces: embedded 5-port 1000/100Base-T/10Base-Te PHY; embedded dual 2.5Gbps/1Gbps SerDes supporting 2500Base-X, SGMII, 1000Base-X, and 100Base-FX; embedded single RGMII, MII, or RMII interface.
• Advanced features: parallel or serial LED output; SPI, MDIO, IIC slave interfaces; MDIO, IIC master interfaces; 1 interrupt output to external CPU for notification; 16K-byte EEPROM space for configuration; cable-length energy saving on link establishment; energy saving on link disconnect; 9K-byte jumbo frames; 2 IEEE 802.3ad link aggregation port groups.
• Security filtering: per-port disable of address learning; per-port disable of learning table aging; unknown destination address filter mask; port isolation; broadcast, multicast, and unknown destination address storm control for system protection against hacking; DoS attack protection.
• Control, management, and statistics: RFC MIB counters including MIB-II, Ethernet-like MIB, Interface Group MIB, RMON, Bridge MIB, and Bridge MIB extensions; OAM and EEE LLDP; loop detection.
• Packet processing engine: 802.1Q VLAN; 4K VLANs; untagged port definition per VLAN; VLAN policing and VLAN forwarding decisions; port-based, tag-based, and protocol-based VLANs; per-port egress VLAN tagging and untagging; IEEE 802.1D/s/w STP; multicast VLAN registration; independent VLAN learning, shared VLAN learning, and hybrid mode; IEEE 802.1ad stacked VLAN; VLAN translation; IEEE 802.1x access control including port-based and MAC-based access control; guest VLAN; ACL rules; hardware or software IGMP/MLD snooping; fast leave; IGMP V1/V2/V3; static or dynamic router ports.
• Mirroring: port-based mirroring; flow-based mirroring; reserved multicast control; Wake-on-LAN.
• QoS: queue-based deficit weighted round-robin (DWRR) or strict priority scheduling with packet or byte mode; min-max queue-based shaping with packet or byte mode; single token bucket for port-based shaping with packet or byte mode; per-port ingress bandwidth control with packet or byte mode; three-color marker in color-aware or color-blind mode with packet or byte mode; traffic classification based on multiple source types; 8 unicast queues and 4 multicast queues per port; tail drop and WRED for unicast queues, tail drop for multicast queues.
• Microprocessor: integrated RISC-V microprocessor; flash interface (dual or single mode); 25MHz crystal or 3.3V OSC input; TQFP 128-pin E-PAD package.

• 5-port 1000Base-T plus 1-port RGMII and 1-port 2500Base-X switch
• 5-port 1000Base-T plus 2-port 2500Base-X, 1000Base-X, or 100Base-FX switch
• 5-port 1000Base-T plus single MII or RGMII interface router