OB OB38R08A1W10MP

The original 8052 uses a 12-clock architecture, where one machine cycle requires 12 clocks, and most instructions take one or two machine cycles. Therefore, except for multiply and divide instructions, each instruction in the 8052 uses 12 or 24 clocks. Furthermore, each cycle in the 8052 performs two memory fetches. In many cases, the second fetch is a dummy fetch, and the extra clocks are wasted. The OB38R08A1 is a high-speed single-chip 8-bit microcontroller core. It is a full-featured 8-bit embedded controller that executes all ASM51 instructions and shares the same instruction set as MCS-51.

• Operating voltage: 2.4V~5.5V
• High-speed 1T architecture, up to 16MHz
• 1~8T mode software programmable
• Instruction set compatible with MCS-51
• Built-in 16MHz RC oscillator with programmable clock divider
• 8KB on-chip programmable program memory
• 512B standard 8052 RAM
• Dual 16-bit data pointers (DPTR0 & DPTR1)
• One full-duplex serial interface with dedicated baud rate generator
• Three 16-bit timers/counters (Timer 0, 1, 2)
• 8~18 GPIOs (10L~20L package pins); GPIOs support four configurable modes (quasi-bidirectional, push-pull, open-drain, input-only), default quasi-bidirectional (pull-up)
• External interrupt 0 & external interrupt 1 with four priority levels
• Programmable watchdog timer (WDT)
• One I²C interface (master/slave mode)
• One SPI interface (master/slave mode)
• 4-channel 10-bit PWM
• 4-channel 16-bit compare (PWM)/capture/reload
• 8-channel 12-bit ADC
• On-chip comparator
• On-chip memory supports ISP/IAP/ICP and EEPROM functions
• ISP service program storage space configurable as N×128 bytes (N = 0 to 8)
• On-chip ICE and OCD support
• Keyboard interrupt (KBI) with 4 interrupt sources
• Low-voltage interrupt/low-voltage reset (LVI/LVR)
• Pin ESD protection exceeding 4KV
• Enhanced user code protection
• Power management unit with idle and power-down modes