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Nexperia 74AUP1T97GW-Q100H product image
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Nexperia 74AUP1T97GW-Q100HRoHS

Manufacturer
Nexperia
MPN
74AUP1T97GW-Q100H
LCSC Part #
C4468770
Packaging
TSSOP-6
Customer #
Key Attributes
Low-power configurable gate with voltage-level translator
Datasheetpdf iconNexperia 74AUP1T97GW-Q100H
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QtyUnit Price(Reference Only)Total Amount
1+$ 0.548$ 0.55
10+$ 0.4673$ 4.67
30+$ 0.4331$ 12.99
100+$ 0.3897$ 38.97
500+$ 0.371$ 185.50
1,000+$ 0.3586$ 358.60
Standard Packaging3000/Full Reel
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters - Multi-Function, Configurable
ManufacturerNexperia
PackagingTSSOP-6
output type-
Logic Family74AUP Series
Input typeSchmitt trigger
Propagation Delay10.8ns@3.3V,30pF
Voltage - Supply2.3V~3.6V
Operating Temperature-40℃~+125℃
Output Logic Level - Low450mV;500mV
Input Logic Level - High-
Input Logic Level - Low-
Current - Output Low(IOL)4mA
Output Logic Level - High2.3V;2.55V
Quiescent Current(Iq)1.5uA
Current - Output High(IOH)4mA
FeaturesLocal shutdown mode;Overvoltage-tolerant input
Number of Gates1
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Introduction

AI Translation

The 74AUP1T97-Q100 is a configurable multiple function gate with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic levels in 3.3 V applications. This device ensures very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features

AI Translation
  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
  • Specified from -40 ℃ to +85 ℃ and from -40 ℃ to +125 ℃
  • Wide supply voltage range from 2.3 V to 3.6 V
  • CMOS low power dissipation
  • High noise immunity
  • Overvoltage tolerant inputs to 3.6 V
  • Low noise overshoot and undershoot <10 % of VCC
  • IOFF circuitry provides partial power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Low static power consumption; ICC = 1.5 μA (maximum)
  • Complies with JEDEC standards: JESD8-12 (1.8 V to 1.3 V), JESD8-11 (1.9 V to 1.65 V), JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V)
  • ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V; CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V